linux.git/drivers/gpu/drm/amd/display/dc/link/protocols, branch v6.12

drm/amd/display: Restructure dpia link training

2024-09-18T20:15:07+00:00

[WHY]
We intend to consolidate dp tunneling and conventional dp link training.

[HOW]
1. Use the same link training entry for both dp and dpia
2. Move SET_CONFIG of non-transparent mode to dmub side
3. Add set_tps_notification dmub_cmd to notify tps request for
   non-transparent dpia link training
4. Check dpcd request result and abort link training early if dpia
   aux tunneling fails
5. Add option to avoid affect old product
6. Separately handle wait_time_microsec for dpia

Reviewed-by: Cruise Hung 
Reviewed-by: George Shen 
Reviewed-by: Meenakshikumar Somasundaram 
Signed-off-by: Peichen Huang 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Implement new DPCD register handling

2024-09-18T20:15:06+00:00

[WHY]
There are some monitor timings that seem to be supported without
DSC but actually require DSC to be displayed. A VESA SCR introduced
a new max uncompressed pixel rate cap register that we can use to
handle these edge cases.

[HOW]
SST: Read caps from link and invalidate timings that exceed the
max limit but do not support DSC. Then check for options override
when determining BPP.

MST: Read caps from virtual DPCD peer device or daisy chained SST
monitor and set validation set BPPs to max if pixel rate exceeds
uncompressed limit. Validation set optimization continues as normal.

Reviewed-by: Wenjing Liu 
Signed-off-by: Ryan Seto 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Support UHBR10 link rate on eDP

2024-08-21T02:14:13+00:00

[why]
Supporting UHBR10 link rate on eDP leverages
the existing DP2.0 code but need to add some small
adjustments in code.

[how]
Acknowledge the given DPCD caps for UHBR10
link rate support and allow DP2.0 programming
sequence and link training for eDP.

Reviewed-by: Wenjing Liu 
Signed-off-by: Sung Joon Kim 
Signed-off-by: Roman Li 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Allow UHBR Interop With eDP Supported Link Rates Table

2024-08-21T02:14:13+00:00

[WHY]
eDP 2.0 is introducing support for UHBR link rates, however current eDP ILR
link optimization does not account for UHBR capabilities.
Either UHBR capabilities will be provided via the same 128b/132b rate DPCD caps
that are currently used on DP2.1, or Table 4-13 may be updated to include UHBR
rates.

[HOW]
Add extra Supported Link Rates table translations for UHBR10/13.5/20.
Update eDP link setting optimization search to be aware of 128b/132b DPCD
rate caps in order to unblock UHBR on panels with Supported Link Rates table.

Reviewed-by: Wenjing Liu 
Signed-off-by: Michael Strauss 
Signed-off-by: Roman Li 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Print Pcon FRL Link BW in Debug Message

2024-08-06T15:11:01+00:00

Under autonomous mode, source reads dpcd DP_PCON_HDMI_POST_FRL_STATUS
for the frl link status.

Without dsc passthrough, it serves as bw bottleneck on the entire link,
compared with the dp link from source to the converter where dsc is
available.

Reviewed-by: Rodrigo Siqueira 
Signed-off-by: Fangzhi Zuo 
Signed-off-by: Wayne Lin 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Check null pointers before used

2024-07-23T21:07:12+00:00

[WHAT & HOW]
Poniters, such as dc->clk_mgr, are null checked previously in the same
function, so Coverity warns "implies that "dc->clk_mgr" might be null".
As a result, these pointers need to be checked when used again.

This fixes 10 FORWARD_NULL issues reported by Coverity.

Reviewed-by: Rodrigo Siqueira 
Signed-off-by: Jerry Zuo 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Replace assert with error message in dp_retrieve_lttpr_cap()

2024-07-23T21:07:09+00:00

[Why]
When assert in dp_retrieve_lttpr_cap() is hit, dmesg has traces like:

 RIP: 0010:dp_retrieve_lttpr_cap+0xcc/0x1a0 [amdgpu]
 Call Trace:
 
  dp_retrieve_lttpr_cap+0xcc/0x1a0 [amdgpu]
  report_bug+0x1e8/0x240
  handle_bug+0x46/0x80
  link_detect+0x35/0x580 [amdgpu]

It happens when LTTPRs fail to increment dpcd repeater count.
We have a recovery action in place for such cases.
Assert is misleading, an indicative error in dmesg is more useful.

[How]
Remove ASSERT and use DC_LOG_ERROR instead.

Reviewed-by: Michael Strauss 
Signed-off-by: Jerry Zuo 
Signed-off-by: Roman Li 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix possible overflow in integer multiplication

2024-07-01T20:06:53+00:00

[WHAT & HOW]
Integer multiplies integer may overflow in context that expects an
expression of unsigned/siged long long (64 bits). This can be fixed
by casting integer to unsigned/siged long long to force 64 bits results.

This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity.

Reviewed-by: Harry Wentland 
Signed-off-by: Jerry Zuo 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Validate function returns

2024-06-27T21:10:38+00:00

[WHAT & HOW]
Function return values must be checked before data can be used
in subsequent functions.

This fixes 4 CHECKED_RETURN issues reported by Coverity.

Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix reduced resolution and refresh rate

2024-06-27T21:10:37+00:00

[WHY]
Some monitors are forced to a lower resolution and refresh rate after
system restarts.

[HOW]
Some monitors may give invalid LTTPR information when queried such as
indicating they have one DP lane instead of 4. If given an invalid DPCD
version, skip over getting lttpr link rate and lane counts.

Reviewed-by: Wenjing Liu 
Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: stable@vger.kernel.org
Signed-off-by: Alex Hung 
Signed-off-by: Daniel Sa 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher