linux.git/drivers/gpu/drm/amd/display/dc/dsc, branch v5.16

drm/amd/display: move FPU associated DSC code to DML folder

2021-10-28T18:26:14+00:00

[Why & How]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate code that uses
FPU in DSC to DML, where all FPU code should locate.

This change does not refactor any functions but move code around.

Cc: Christian König 
Cc: Hersen Wu 
Cc: Anson Jacob 
Cc: Harry Wentland 
Reviewed-by: Rodrigo Siqueira 
Acked-by: Agustin Gutierrez 
Tested-by: Anson Jacob 
Tested-by: Daniel Wheeler 
Signed-off-by: Qingqing Zhuo 
Acked-by: Christian König 
Signed-off-by: Alex Deucher

drm/amd/display: move bpp range decision in decide dsc bw range function

2021-09-14T19:57:09+00:00

[why]
Before get dsc bw range is used to compute DSC bw range
based on the given fixed bpp min/max input.
The new change will merge any specs, signal, timing specific
bpp range decision into this function. So the function needs to make
a decision with all aspects considered.

Acked-by: Mikita Lipski 
Signed-off-by: Wenjing Liu 
Reviewed-by: George Shen 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: expose dsc overhead bw in dc dsc header

2021-09-14T19:56:50+00:00

[why]
DM needs to know how much overhead is added to DSC as result
of AMD internal DSC limitation.

Acked-by: Mikita Lipski 
Signed-off-by: Wenjing Liu 
Reviewed-by: George Shen 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fixed EdidUtility build errors

2021-07-28T20:37:17+00:00

[HOW]
Added #ifdefs and refactored various parts of dc to
allow dc_link to be built by AMD EDID UTILITY

[WHY]
dc_dsc was refactored moving some of the code that AMD EDID UTILITY needed
to dc_link, so now dc_link needs to be included by AMD EDID UTILITY

Squash in DCN config fix (Alex)

Reviewed-by: Leung Martin 
Acked-by: Solomon Chiu 
Signed-off-by: Mark Morra 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: add dsc stream overhead for dp only

2021-05-10T22:06:44+00:00

[why]
Based on hardware team recommendation this additional dsc overhead
is only required for DP DSC.

[how]
Add a check for is_dp and only apply the overhead if this flag is set.

Signed-off-by: Wenjing Liu 
Reviewed-by: Chris Park 
Acked-by: Wayne Lin 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: take max dsc stream bandwidth overhead into account

2021-04-29T03:35:50+00:00

[why]
As hardware team suggested that we need to add a max dsc bw overhead
into existing stream bandwidth when DSC is used.
The formula as below:

max_dsc_bw_overhead =
v_addressable * slice_count * 256 bit * pixel clock / v_total / h_total

effective stream bandwidth = pixel clock * bpp

stream bandwidth = effective stream bandwidth + dsc stream overhead

Signed-off-by: Wenjing Liu 
Reviewed-by: Eric Bernstein 
Acked-by: Wayne Lin 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations

2021-03-24T03:32:31+00:00

[Why?]
Some code still expected bpp to be used in whole bits, not 16ths.  dsc.c uses
redundant function now found in dc to calculate stream bandwidth from timing.

[How?]
Fix code to work with 16ths instead of whole bits for dsc bpp.
Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit.
Use dc function to calculate bandwidth from timing, and make dsc bw calculation
a part of dsc.c.

Tested-by: Daniel Wheeler 
Signed-off-by: Dillon Varone 
Reviewed-by: Wenjing Liu 
Acked-by: Solomon Chiu 
Signed-off-by: Alex Deucher

drm/amd/display: revert support for DID2.0 dsc passthrough

2021-02-09T20:31:07+00:00

3x4K60 displays over MST with DSC enabled was not able to light up
due to this patch.

Signed-off-by: Jun Lei 
Reviewed-by: Anthony Koo 
Acked-by: Anson Jacob 
Signed-off-by: Alex Deucher

drm/amd/display: implement support for DID2.0 dsc passthrough

2021-02-02T17:10:48+00:00

[Why]
Some panels contain active converters (e.g. DP to MIPI) which only support
restricted DSC configurations.  DID2.0 adds support for such displays to
explicitly define per timing BPP restrictions on DSC.  Ignoring these
restrictions leads to blackscreen.

[How]
Add parsing in DID2.0 parser to get this bpp info.
Add support in DSC module to constraint target bpp based
on this info.

Signed-off-by: Jun Lei 
Reviewed-by: Wenjing Liu 
Acked-by: Anson Jacob 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amdgpu/display: drop DCN support for aarch64

2021-01-05T16:35:53+00:00

From Ard:

"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
and GCC is known to use SIMD registers for spilling, and may invent
other uses of the FP/SIMD register file that have nothing to do with the
floating point code in question. Note that putting kernel_neon_begin()
and kernel_neon_end() around the code that does use FP is not sufficient
here, the problem is in all the other code that may be emitted with
references to SIMD registers in it.

So the only way to do this properly is to put all floating point code in
a separate compilation unit, and only compile that unit with
-mgeneral-regs-only."

Disable support until the code can be properly refactored to support this
properly on aarch64.

Acked-by: Will Deacon 
Reported-by: Ard Biesheuvel 
Signed-off-by: Alex Deucher