linux.git/drivers/gpu/drm/amd/display/dc/dml, branch v6.1

drm/amd/display: fix array index out of bound error in DCN32 DML

2022-12-07T17:21:53+00:00

[Why&How]
LinkCapacitySupport array is indexed with the number of voltage states and
not the number of max DPPs. Fix the error by changing the array
declaration to use the correct (larger) array size of total number of
voltage states.

Signed-off-by: Aurabindo Pillai 
Reviewed-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org # 6.0.x

drm/amd/display: Use new num clk levels struct for max mclk index

2022-11-23T14:01:53+00:00

[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.

[HOW?]
Use num_memclk_level from num_entries_per_clk struct for getting the correct max
mem speed.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Update soc bounding box for dcn32/dcn321

2022-11-23T14:01:53+00:00

[Description]
New values for soc bounding box and dummy pstate.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org # 6.0.x

drm/amd/display: Set max for prefetch lines on dcn32

2022-11-15T18:22:50+00:00

[WHY?]
Max number of lines that can be used for prefetch due to type constraints is
63.75.

[HOW?]
Enforce maximum prefetch lines as 63.75.

Reviewed-by: Jun Lei 
Acked-by: Tom Chung 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: use uclk pstate latency for fw assisted mclk validation dcn32

2022-11-15T18:22:20+00:00

[WHY?]
DCN32 uses fclk pstate watermarks for dummy pstate, and must always be
supported.

[HOW?]
Validation needs to be run with fclk pstate latency set
as the dummy pstate latency to get correct prefetch and bandwidth outputs.

Reviewed-by: Jun Lei 
Acked-by: Tom Chung 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix prefetch calculations for dcn32

2022-11-15T18:21:30+00:00

[Description]
Prefetch calculation loop was not exiting until utilizing all of vstartup if it
failed once.  Locals need to be reset on each iteration of the loop.

Reviewed-by: Jun Lei 
Acked-by: Tom Chung 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org # 6.0.x

drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32

2022-11-09T23:04:13+00:00

[WHY?]
Data return times when using lowest memclk can be <= 60us, which can cause
underflow on high bandwidth displays with a workload.

[HOW?]
Enforce a minimum prefetch time during validation for low memclk modes.

Reviewed-by: Jun Lei 
Acked-by: Alan Liu 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix FCLK deviation and tool compile issues

2022-11-09T23:01:47+00:00

[Why]
Recent backports from open source do not have header inclusion pattern
that is consistent with inclusion style in the rest of the file. This
breaks the internal tool builds as well. A recent commit erronously
modified the original DML formula for calculating
ActiveClockChangeLatencyHidingY. This resulted in a FCLK deviation
from the golden values.

[How]
Change the way in which display_mode_vba.h is included so that it is
consistent with the inclusion style in rest of the file which also fixes
the tool build. Restore the DML formula to its original state to fix the
FCLK deviation.

Reviewed-by: Aurabindo Pillai 
Reviewed-by: Jun Lei 
Acked-by: Alan Liu 
Signed-off-by: Chaitanya Dhere 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Zeromem mypipe heap struct before using it

2022-11-09T23:00:11+00:00

[Why&How]
Bug was caused when moving variable from stack to heap because it was reusable
and garbage was left over, so we need to zero mem.

Reviewed-by: Martin Leung 
Acked-by: Alan Liu 
Signed-off-by: Aurabindo Pillai 
Signed-off-by: Martin Leung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Update SR watermarks for DCN314

2022-11-09T22:59:10+00:00

[Why & How]
New values requested by hardware after fine-tuning.
Update for all memory types.

Reviewed-by: Jun Lei 
Acked-by: Alan Liu 
Signed-off-by: Nicholas Kazlauskas 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org # 6.0.x