linux.git/drivers/gpu/drm/amd/display/dc/dml, branch v5.9

drm/amd/display: fix dcn3 wide timing dsc validation

2020-08-18T21:58:19+00:00

Wide timing DSC requires odm. Since spreadsheet is missing this dsc
validation we have to modify DML vba code ourselves.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Wesley Chalmers 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: populate new dml variable

2020-08-06T20:48:07+00:00

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Clean up global sync param retrieval

2020-08-06T20:37:35+00:00

[Why]
This change replaces older looping code in favor of these functions.

[How]
There are built in functions for extracting global sync params
during mode validation now.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Eryk Brol 
Signed-off-by: Alex Deucher

drm/amd/display: fix dcn3 p_state_change_support validation (v2)

2020-07-14T18:37:33+00:00

Our validation is a known mess with actual validation mixed with
topology configuration. This change makes sure topolgical validation is
completed before any topology changes are made so we do not run into
issues where we merge and split a pipe over the course of a single call.

v2: Squash in compilation fix

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Alvin Lee 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: update dml var

2020-07-14T18:33:56+00:00

Update *DynamicMetadata variables for providing more flexibility.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Harry Wentland 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Allow 4 split on 10K 420 modes

2020-07-01T05:59:26+00:00

[Why]
10K YCbCr420 does not need ODM 4:1, but it requires MPC 4 split
indicated on the flags.

[How]
Make pixel encoding and resolution size specific workaround to enable
ODM combine on YCbCr420 high resolution modes.

Signed-off-by: Chris Park 
Reviewed-by: Charlene Liu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Force ODM combine on 5K+ 420 modes

2020-07-01T05:59:25+00:00

[Why]
All YCbCr420 resolutions 5K and above have tiling and discoloration
issues.  The issue can be remedied by forcing ODM combine from 5K to 8K.
10K resolution requires ODM 4:1.  The mechanism of what the real problem
is, that is inherent in ODM combine programming, doesn't seem to be
pointed at singular register programming (CLK, MPC, DCSURF, etc.), and
needs more in-depth programming sequence review for these new use case
scenarios.  Until then, workaround to enable ODM combine is proposed.
While it is not our policy, HW spreadsheet also recommends turning on
ODM for these scenario to lower the voltage.

[How]
Make pixel encoding and resolution size specific workaround to enable
ODM combine on YCbCr420 high resolution modes.

Signed-off-by: Chris Park 
Reviewed-by: Charlene Liu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Fix VBA chroma calculation for pipe splitting

2020-07-01T05:59:20+00:00

[Why]
DML failures occur for 420 modes with dynamic pipe
splitting enabled because the ChromaViewport exceeds
the ChromaSurfaceWidth.

This is caused by adding the viewport_width instead
of the viewport_width_c.

This similarly occurs for rotated modes due to the
use of viewport_height instead of viewport_height_c.

[How]
Correct the calculations.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Qingqing Zhuo 
Signed-off-by: Alex Deucher

drm/amd/display: fix spelling mistake: "propogation" -> "propagation"

2020-07-01T05:59:16+00:00

There is a spelling mistake in a dml_print message. Fix it.

Signed-off-by: Colin Ian King 
Signed-off-by: Alex Deucher

drm/amd/display: Add DCN3 DML

2020-07-01T05:59:14+00:00

Add support for DML(Display mode library) for bandwidth calculations

Signed-off-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher