linux.git/drivers/gpu/drm/amd/display/dc/dml2, branch v6.17

drm/amd/display: Refactor DML21 Initialization and Configuration

2025-06-30T15:58:50+00:00

[Why & How]
- Consolidated the initialization of DML21 parameters into a single
function `dml21_populate_dml_init_params` to streamline the process
and improve code readability.
- Updated the function signatures in the header files to reflect changes
in parameter passing for DML context.
- Removed redundant debug option handling and integrated it into the new
configuration population function.
- Adjusted the DML21 initialization logic in the wrapper to accommodate
the new structure, ensuring compatibility with different DCN versions.
- Enhanced the handling of clock parameters and bounding box configurations
from various sources, including hardware defaults and software policies.
- Improved the clarity of the code by renaming functions and variables for
better understanding of their purposes.

Reviewed-by: Austin Zheng 
Signed-off-by: Wenjing Liu 
Signed-off-by: Ray Wu 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: DML21 Reintegration

2025-06-24T13:58:07+00:00

Update logging macros for detailed debugging
Update structs to contain more detailed information
Add HDMI 16 and 20 Gbps rates

Reviewed-by: Alvin Lee 
Signed-off-by: Austin Zheng 
Signed-off-by: Fangzhi Zuo 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Removed unnecessary comment

2025-06-24T13:55:30+00:00

Reviewed-by: Sridevi Arvindekar 
Signed-off-by: Alvin Lee 
Signed-off-by: Fangzhi Zuo 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Include EQU Prefetch Bandwidth For Bandwidth Calculations

2025-06-24T13:55:22+00:00

[Why]
Pixel data bandwidth required in mode programming (MP) ends up being
higher than what was calculated in mode support (MS) even though
the prefetch bandwidths calculated in MP are lower than the MS ones.

MP used a different equ prefetch schedule than MS which lead a
slight difference in parameters. This resulted in the pixel data
bandwidth in MP to be higher than MS.

[How]
Rename the RequiredPrefetchBWOTO term so it can be applied generically.
Update the value with the EQU bandwidth if the EQU schedule is used.
Get the max prefetch bandwidth that MS calculated and use it
as part of the calculations for required bandwidth.

Reviewed-by: Dillon Varone 
Signed-off-by: Austin Zheng 
Signed-off-by: Fangzhi Zuo 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: remove use_native_pstate_optimization

2025-06-18T16:19:20+00:00

[Why]
In DML2 (not DML2.1), DCN35 and DCN351 have the
default value for use_native_pstate_optimization
set to true. The code path where this bit is
false is not used.

[How]
Remove the bit and the corresponding code path
when it is set to false.

Reviewed-by: Nicholas Kazlauskas 
Reviewed-by: Aric Cyr 
Signed-off-by: Yan Li 
Signed-off-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: apply two different methods to validate modes

2025-06-18T16:19:19+00:00

[Why]
In DML2, the current method to determine a
mode is supported involves checking the
voltage levels sequentially from the lowest,
until one is found that can support the
mode. It causes cursor lag due to low
performance.

[How]
We apply two methods for mode validation.
1) DC_VALIDATE_MODE_ONLY: only the
maximum voltage level is checked to
determine whether the mode is supported, which
improves performance and eliminate cursor lag.

2) DC_VALIDATE_MODE_AND_STATE_INDEX: when
the optimal voltage level is required, check
the voltage level from the lowest until
a suitable one is found found and returns
its index.

Reviewed-by: Nicholas Kazlauskas 
Reviewed-by: Aric Cyr 
Signed-off-by: Yan Li 
Signed-off-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Fix RMCM programming seq errors

2025-06-18T16:19:17+00:00

[WHY & HOW]
Fix RMCM programming sequence errors and mapping issues to pass the RMCM
test.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Reviewed-by: Dmytro Laktyushkin 
Signed-off-by: Yihan Zhu 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: DML2.1 changes

2025-06-18T16:19:17+00:00

* Add a missing compilation unit
* Missing CFLAGS for certain units

Reviewed-by: Roman Li 
Signed-off-by: Aurabindo Pillai 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix mpv playback corruption on weston

2025-06-18T16:19:17+00:00

[WHAT]
Severe video playback corruption is observed in the following setup:

weston 14.0.90 (built from source) + mpv v0.40.0 with command:
mpv bbb_sunflower_1080p_60fps_normal.mp4 --vo=gpu

[HOW]
ABGR16161616 needs to be included in dml2/2.1 translation.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Acked-by: Aurabindo Pillai 
Reviewed-by: Harry Wentland 
Reviewed-by: Austin Zheng 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Deprecate Loading Bounding Box From DMUB On DCN4

2025-06-18T16:19:16+00:00

[WHY]
dml2_soc_bb struct can continuously receive updates for future ASICs.
Alignment issues may arise since VBIOS DMCUB contains an older version of
the SOC BB.

Populating the bounding box with values from DMCUB is no longer necessary
since values such as UCLK will be overridden by values acquired by PMFW
anyways.

[HOW]
Use bb_from_dmub to store DCN specific bounding box parameters in DMCUB.
Add helpers to translate DCN specific struct to the corresponding
dml2_soc_bb field.

To avoid alignment issues:
Deprecate applying DMCUB SoC BB for DCN4

For future projects:
Create a flattened struct containing all sensitive parameters in the
bounding box. New parameters can be added to the bottom of the new struct
as needed.

Reviewed-by: Dillon Varone 
Signed-off-by: Austin Zheng 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher