<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/gpu/drm/amd/display/dc/dio, branch master</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>drm/amd/display: switch max FFE level cap based on FRL link rate</title>
<updated>2026-08-06T16:44:20+00:00</updated>
<author>
<name>Relja Vojvodic</name>
<email>Relja.Vojvodic@amd.com</email>
</author>
<published>2026-07-13T20:04:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=047f60370f7071194949492261f91bd475f66755'/>
<id>047f60370f7071194949492261f91bd475f66755</id>
<content type='text'>
[How &amp; Why]
- Add support for dynamic FFE levels based on debug config and link rate

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Relja Vojvodic &lt;Relja.Vojvodic@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[How &amp; Why]
- Add support for dynamic FFE levels based on debug config and link rate

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Relja Vojvodic &lt;Relja.Vojvodic@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Enable DCN6 sources compilation</title>
<updated>2026-08-06T13:53:32+00:00</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2026-07-21T13:59:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=992694ad28584188725751f695a85661e8e3797a'/>
<id>992694ad28584188725751f695a85661e8e3797a</id>
<content type='text'>
- Add hooks in various entry points to perform hw/sw init for DCN6 asic
- Add dependent changes needed to enable DCN6 asic
- Update the Makefiles so that DCN6 related newly added sources are compiled

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Reviewed-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- Add hooks in various entry points to perform hw/sw init for DCN6 asic
- Add dependent changes needed to enable DCN6 asic
- Update the Makefiles so that DCN6 related newly added sources are compiled

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Reviewed-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Add new sources for DCN6</title>
<updated>2026-08-06T13:48:29+00:00</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2026-07-22T18:45:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7f7d7ea1fa515157162d0d21245925551ed103a1'/>
<id>7f7d7ea1fa515157162d0d21245925551ed103a1</id>
<content type='text'>
Add DCN6 code to DC, DML2, and DMUB

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Reviewed-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add DCN6 code to DC, DML2, and DMUB

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Reviewed-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: add null pointer access check</title>
<updated>2026-07-14T23:12:35+00:00</updated>
<author>
<name>Charlene Liu</name>
<email>Charlene.Liu@amd.com</email>
</author>
<published>2026-06-22T20:29:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b6f466c509ad2f390b3fc91cd0de4783554f5f98'/>
<id>b6f466c509ad2f390b3fc91cd0de4783554f5f98</id>
<content type='text'>
[why]
need to add null pointer access check

Reviewed-by: Gabe Teeger &lt;gabe.teeger@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: George Zhang &lt;george.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[why]
need to add null pointer access check

Reviewed-by: Gabe Teeger &lt;gabe.teeger@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: George Zhang &lt;george.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: correct encoder minimal creation</title>
<updated>2026-07-01T15:34:15+00:00</updated>
<author>
<name>Peichen Huang</name>
<email>PeiChen.Huang@amd.com</email>
</author>
<published>2026-06-16T02:37:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e14fcf9e5d2b521bec0ea3051058e64add87cb21'/>
<id>e14fcf9e5d2b521bec0ea3051058e64add87cb21</id>
<content type='text'>
[WHY]
shift and mask are not correctly initialized in create_minimal functions.

[HOW]
Correct initialize necessary variables.

Reviewed-by: Cruise Hung &lt;cruise.hung@amd.com&gt;
Signed-off-by: Peichen Huang &lt;PeiChen.Huang@amd.com&gt;
Signed-off-by: George Zhang &lt;george.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY]
shift and mask are not correctly initialized in create_minimal functions.

[HOW]
Correct initialize necessary variables.

Reviewed-by: Cruise Hung &lt;cruise.hung@amd.com&gt;
Signed-off-by: Peichen Huang &lt;PeiChen.Huang@amd.com&gt;
Signed-off-by: George Zhang &lt;george.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL</title>
<updated>2026-06-03T17:44:31+00:00</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2026-04-24T16:17:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=d36771a03412454a0c7f1c81746426958008a2bb'/>
<id>d36771a03412454a0c7f1c81746426958008a2bb</id>
<content type='text'>
This adds support to HW block programming for the core blocks
for HDMI FRL:
- DIO
- HPO
- OPP
- OPTC

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds support to HW block programming for the core blocks
for HDMI FRL:
- DIO
- HPO
- OPP
- OPTC

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCN42B code to DC</title>
<updated>2026-06-03T17:44:02+00:00</updated>
<author>
<name>Matthew Stewart</name>
<email>matthew.stewart2@amd.com</email>
</author>
<published>2026-05-18T19:00:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0a5e0416e191571de9362b769feb31b3e87a705e'/>
<id>0a5e0416e191571de9362b769feb31b3e87a705e</id>
<content type='text'>
[Why &amp; How]
Add DCN42B code to DC

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;Matthew.Stewart2@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why &amp; How]
Add DCN42B code to DC

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;Matthew.Stewart2@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Fix DP_PIXEL_FORMAT fields &amp; update clk_src for DCN4x</title>
<updated>2026-06-03T17:39:58+00:00</updated>
<author>
<name>Ovidiu Bunea</name>
<email>ovidiu.bunea@amd.com</email>
</author>
<published>2026-05-14T21:39:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c2572d535be4847f8caba58b4ee8446b4ee15b57'/>
<id>c2572d535be4847f8caba58b4ee8446b4ee15b57</id>
<content type='text'>
[Why &amp; How]
The enc1_stream_encoder_dp_get_pixel_format() function reads fields of the
DP_PIXEL_FORMAT register that are deprecated on DCN4x. This breaks seamless
boot because driver cannot properly determine the pixel format programmed by VBIOS.
The previous changed submitted for this issue incorrectly calculated the DP DTO
frequency because register access to DCN4x DP DTO registers was not working.

Create a new function that reads the correct fields.
Update clk_src structs to support register access for new DCN4x registers &amp; fields.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Ovidiu Bunea &lt;ovidiu.bunea@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why &amp; How]
The enc1_stream_encoder_dp_get_pixel_format() function reads fields of the
DP_PIXEL_FORMAT register that are deprecated on DCN4x. This breaks seamless
boot because driver cannot properly determine the pixel format programmed by VBIOS.
The previous changed submitted for this issue incorrectly calculated the DP DTO
frequency because register access to DCN4x DP DTO registers was not working.

Create a new function that reads the correct fields.
Update clk_src structs to support register access for new DCN4x registers &amp; fields.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Ovidiu Bunea &lt;ovidiu.bunea@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Fix warnings</title>
<updated>2026-05-11T20:10:34+00:00</updated>
<author>
<name>Clay King</name>
<email>clayking@amd.com</email>
</author>
<published>2026-04-27T18:51:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c3fb1fb9e65fa6a108b4d19c61bdcb47fd4fe180'/>
<id>c3fb1fb9e65fa6a108b4d19c61bdcb47fd4fe180</id>
<content type='text'>
[Why &amp; How]
Fix various warnings related to unsigned/signed mismatches
-  Consistently use the same signedness for a given value
-  Explcitly cast between types when needed

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Clay King &lt;clayking@amd.com&gt;
Signed-off-by: James Lin &lt;pinglei.lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why &amp; How]
Fix various warnings related to unsigned/signed mismatches
-  Consistently use the same signedness for a given value
-  Explcitly cast between types when needed

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Clay King &lt;clayking@amd.com&gt;
Signed-off-by: James Lin &lt;pinglei.lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Fix type mismatches using guards and explicit casts</title>
<updated>2026-05-05T13:56:52+00:00</updated>
<author>
<name>Gaghik Khachatrian</name>
<email>gaghik.khachatrian@amd.com</email>
</author>
<published>2026-04-21T16:24:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=64b4c4cdfddd31d3a0ec468afccb7ff7cd926682'/>
<id>64b4c4cdfddd31d3a0ec468afccb7ff7cd926682</id>
<content type='text'>
[Why]
Address signed/unsigned comparison warnings across dc paths to keep
builds warning-clean and improve type safety at comparison boundaries.
Most warnings came from signed loop/index temporaries compared against
unsigned counters and table sizes, plus a smaller number of mixed
signed/unsigned clock, bandwidth, and geometry comparisons.

[How]
Aligned iterator and temporary variable types with the semantic type
of the compared bounds. Used unsigned indices for loops bounded by unsigned
counters and table sizes, while retaining signed types where values are
semantically signed or participate in arithmetic that may legitimately go
negative. Where mixed signed/unsigned comparisons are intentional, applied
explicit boundary casts or guarded comparisons instead of broad type
changes.

No functional behavior changes are intended; this is a warning-resolution
and type-alignment cleanup.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Gaghik Khachatrian &lt;gaghik.khachatrian@amd.com&gt;
Signed-off-by: James Lin &lt;pinglei.lin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why]
Address signed/unsigned comparison warnings across dc paths to keep
builds warning-clean and improve type safety at comparison boundaries.
Most warnings came from signed loop/index temporaries compared against
unsigned counters and table sizes, plus a smaller number of mixed
signed/unsigned clock, bandwidth, and geometry comparisons.

[How]
Aligned iterator and temporary variable types with the semantic type
of the compared bounds. Used unsigned indices for loops bounded by unsigned
counters and table sizes, while retaining signed types where values are
semantically signed or participate in arithmetic that may legitimately go
negative. Where mixed signed/unsigned comparisons are intentional, applied
explicit boundary casts or guarded comparisons instead of broad type
changes.

No functional behavior changes are intended; this is a warning-resolution
and type-alignment cleanup.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Gaghik Khachatrian &lt;gaghik.khachatrian@amd.com&gt;
Signed-off-by: James Lin &lt;pinglei.lin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
