linux.git/drivers/gpu/drm/amd/display/dc/dccg, branch master Linux kernel source tree treewide: refresh kmalloc_obj() conversions 2026-09-05T04:37:00+00:00 Kees Cook kees+treewide@kernel.org 2026-09-02T22:31:14+00:00 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook <kees+treewide@kernel.org> 
This is another run of the Coccinelle script for converting kmalloc()
family of allocations to kmalloc_obj() via the existing rules in
scripts/coccinelle/api/kmalloc_objs.cocci

This catches both the set of kmalloc() uses added since the first
kmalloc_obj() conversions in v7.0 and adds a large group missed in the
first pass due to Coccinelle not interacting well with the cleanup.h
scoped_...() family of macros[1]. I worked around this with spatch's
"--macro-file" argument to a file with all the scoped_...() macros mapped
to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control
flow indicator I could find.

Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc,
riscv, and s390 with no new warnings.

Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1]
Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2]
Signed-off-by: Kees Cook <kees+treewide@kernel.org>
drm/amd/display: Enable DCN6 sources compilation 2026-08-06T13:53:32+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2026-07-21T13:59:35+00:00 992694ad28584188725751f695a85661e8e3797a - Add hooks in various entry points to perform hw/sw init for DCN6 asic - Add dependent changes needed to enable DCN6 asic - Update the Makefiles so that DCN6 related newly added sources are compiled Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
- Add hooks in various entry points to perform hw/sw init for DCN6 asic
- Add dependent changes needed to enable DCN6 asic
- Update the Makefiles so that DCN6 related newly added sources are compiled

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add new sources for DCN6 2026-08-06T13:48:29+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2026-07-22T18:45:53+00:00 7f7d7ea1fa515157162d0d21245925551ed103a1 Add DCN6 code to DC, DML2, and DMUB Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add DCN6 code to DC, DML2, and DMUB

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: fix wrong register field in dccg35_set_hdmistreamclk_src_new 2026-07-15T13:15:43+00:00 Dyllan Kobal dyllan.kobal@zetier.com 2026-06-23T00:58:04+00:00 db9c882f83d3f3e08069f52d0d2ebf9d131c9ae4 dccg35_set_hdmistreamclk_src_new() updates HDMISTREAMCLK_CNTL but passes DPSTREAMCLK0_SRC_SEL as the field identifier in the second REG_UPDATE_2 slot. The current behavior is harmless on DCN3.5 because both fields share the same bit layout, but it is still incorrect and could break on future hardware revisions. Fixes: d36771a03412 ("drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL") Signed-off-by: Dyllan Kobal <dyllan.kobal@zetier.com> Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
dccg35_set_hdmistreamclk_src_new() updates HDMISTREAMCLK_CNTL but
passes DPSTREAMCLK0_SRC_SEL as the field identifier in the second
REG_UPDATE_2 slot.

The current behavior is harmless on DCN3.5 because both fields share the
same bit layout, but it is still incorrect and could break on future
hardware revisions.

Fixes: d36771a03412 ("drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL")
Signed-off-by: Dyllan Kobal <dyllan.kobal@zetier.com>
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: enable hdmistreamclk_rcg by default for dcn42 2026-07-15T13:15:40+00:00 Charlene Liu Charlene.Liu@amd.com 2026-06-26T20:31:22+00:00 47c9c743ecc248641be6ad03a93307108d855bf0 [why] enable hdmistreamclk_rcg by default Reviewed-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[why]
enable hdmistreamclk_rcg by default

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: ensure dtbclk clk_src selected before hdmistream_clk_en 2026-07-14T23:12:35+00:00 Charlene Liu Charlene.Liu@amd.com 2026-06-24T22:54:43+00:00 5b7e4ad090f2700bfad37f43e4d3553b71be3591 [why] correct a sequence issue by switching to dcn35's dccg sequence: to make sure select dtbclk src first before programming hdmistream_clk_en. Reviewed-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[why]
correct a sequence issue by switching to dcn35's dccg sequence:
to make sure select dtbclk src first before programming hdmistream_clk_en.

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Update ONO PG Workaround for DCN42 2026-07-01T15:17:42+00:00 Leo Chen leo.chen@amd.com 2026-06-09T22:38:23+00:00 3754bdca435c8d38111b46467f82756e36465a58 [Why & How] There is an updated workaround for PG Repeater issue in DCN42. This PR is addressing the dynamic power gating use cases (Driver PG) to align with the new sequence. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why & How]
There is an updated workaround for PG Repeater issue in DCN42. This PR is
addressing the dynamic power gating use cases (Driver PG) to align with
the new sequence.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Disable DPPCLK RCG to fix cursor disappearing 2026-07-01T15:17:19+00:00 Karen Chen Karen.Chen@amd.com 2026-06-10T17:40:13+00:00 687bd7c811ca1ad44785399f02947521a885ca36 [Why & How] DPP clock is gated when programming the cursor. This change disables DPPCLK RCG in dccg42_init before accessing DPP, ensuring cursor programming latches correctly. Assisted-by: Cursor Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Karen Chen <Karen.Chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why & How]
DPP clock is gated when programming the cursor. This change
disables DPPCLK RCG in dccg42_init before accessing DPP,
ensuring cursor programming latches correctly.

Assisted-by: Cursor
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Karen Chen <Karen.Chen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove DCCG registers not needed in DCN42 2026-07-01T15:16:57+00:00 Matthew Stewart Matthew.Stewart2@amd.com 2026-06-05T19:05:46+00:00 dac8aa629a45e34027444f74d3b86b6f104b024c [why] Some resources that exist in the DCN block are not needed and shouldn't be used. [how] Remove defines from register lists. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[why]

Some resources that exist in the DCN block are not needed and shouldn't
be used.

[how]

Remove defines from register lists.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Rewrite dccg42_init 2026-07-01T15:16:45+00:00 Matthew Stewart Matthew.Stewart2@amd.com 2026-06-08T15:22:02+00:00 46fda8bda6f93a38db8ea8cca6d84eae304deff3 [why] DCN42 reuses dccg42_init, which causes problems due to undefined masks. [how] - Read res_pool to determine the quantities of the respective resources - Remove the physymclk root_clock_optimization check, as it seems like it shouldn't do anything (defaults to disabled already). Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[why]

DCN42 reuses dccg42_init, which causes problems due to undefined masks.

[how]

- Read res_pool to determine the quantities of the respective resources
- Remove the physymclk root_clock_optimization check, as it seems like
  it shouldn't do anything (defaults to disabled already).

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>