linux.git/drivers/gpu/drm/amd/display/dc/core, branch master

Merge tag 'kmalloc_obj-v7.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux

2026-09-06T03:45:18+00:00

Pull kmalloc_obj conversions from Kees Cook:
 "Another run of the Coccinelle script for converting kmalloc()
  family of allocations to kmalloc_obj() via the existing rules
  in scripts/coccinelle/api/kmalloc_objs.cocci"

* tag 'kmalloc_obj-v7.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux:
  treewide: refresh kmalloc_obj() conversions
  drm/amd/display: Fix harmless type mismatch in allocation

treewide: refresh kmalloc_obj() conversions

2026-09-05T04:37:00+00:00

This is another run of the Coccinelle script for converting kmalloc()
family of allocations to kmalloc_obj() via the existing rules in
scripts/coccinelle/api/kmalloc_objs.cocci

This catches both the set of kmalloc() uses added since the first
kmalloc_obj() conversions in v7.0 and adds a large group missed in the
first pass due to Coccinelle not interacting well with the cleanup.h
scoped_...() family of macros[1]. I worked around this with spatch's
"--macro-file" argument to a file with all the scoped_...() macros mapped
to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control
flow indicator I could find.

Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc,
riscv, and s390 with no new warnings.

Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1]
Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2]
Signed-off-by: Kees Cook

drm/amd/display: Fix cursor disable with horizontally split planes

2026-09-02T21:02:04+00:00

[WHY]
resource_can_pipe_disable_cursor() disables the hardware cursor on a
pipe when a higher layer fully covers that pipe's recout, to avoid
double-cursor and scaling artifacts.

When merging pipe-split halves of the same overlay layer, the inner
loop walks every pipe above the current one and looks for siblings
sharing test_pipe's layer_index. Because test_pipe itself satisfies
that condition, it can be treated as its own split partner. That
incorrectly doubles r2.width and makes the covering check succeed even
when the overlay does not fully contain the underlying pipe.

On horizontally split or multi-quadrant layouts this causes the cursor
to disappear over overlay regions while input/coordinate mapping remains
correct.

[HOW]
Skip test_pipe when searching for a pipe-split sibling on the same
layer, so only the other half of the split plane is merged into r2.

Signed-off-by: Yuling Li 
Reviewed-by: Leo Li 
Signed-off-by: Alex Deucher 
(cherry picked from commit 85ccd2c39cca9351d4db393e24acea8bf943d350)

drm/amd/display: fix BT.2020 YCbCr limited output CSC matrix

2026-08-12T13:42:44+00:00

COLOR_SPACE_YCBCR2020_TYPE, which is selected for
COLOR_SPACE_2020_YCBCR_LIMITED color_space, has coefficients that are
incorrect for limited-range output. Its luma and chroma scaling is
full-range so output is too bright and colors are incorrect.

COLOR_SPACE_YCBCR2020_TYPE is closer to a full-range conversion matrix with
incorrect luma offset, so correct the luma offset for full-range and rename
it to COLOR_SPACE_YCBCR2020_FULL_TYPE.

Add COLOR_SPACE_YCBCR2020_LIMITED_TYPE with correct scaling and range for
limited-range output.

Fix related functions so COLOR_SPACE_YCBCR2020_LIMITED_TYPE and
COLOR_SPACE_YCBCR2020_FULL_TYPE are correctly selected based on
dc_color_space.

Derivation of both matrices follows ITU-T H.273:

Table 4, MatrixCoefficients 9, BT.2020-NCL weights:
KR = 0.2627, KB = 0.0593, KG = 1 - KR - KB = 0.6780.

Equations 45-47 in matrix form:
            [  KR             KG             KB            0 ]
M2020_NCL = [ -KR/(2(1-KB))  -KG/(2(1-KB))   1/2           0 ]
            [  1/2           -KG/(2(1-KR))  -KB/(2(1-KR))  0 ]
            [  0              0              0             1 ]

Limited and Full transforms based on equations 30-32 and 36-38 with bit
depth 10, normalized by 1023:

            [ 876/1023   0         0         64/1023  ]
MLimited  = [ 0          896/1023  0         512/1023 ]
            [ 0          0         896/1023  512/1023 ]
            [ 0          0         0         1        ]

            [ 1023/1023  0         0         0        ]
    MFull = [ 0          1023/1023 0         512/1023 ]
            [ 0          0         1023/1023 512/1023 ]
            [ 0          0         0         1        ]

M2020_NCL_Limited = MLimited x M2020_NCL
M2020_NCL_Full    = MFull x M2020_NCL

The upper three rows of M2020_NCL_* are stored in CR, Y, CB order. Each
M2020_NCL_* value is stored as Round(value * 8192) in its 16-bit
two's-complement representation.

Fixes: 973a9c810c78 ("drm/amd/display: Fix COLOR_SPACE_YCBCR2020_TYPE matrix")
Assisted-by: OpenAI-Codex:GPT-5.6-Sol
Tested-by: Igor Paunovic 
Tested-by: Satyajit Roy 
Signed-off-by: Nathan Lucas 
Signed-off-by: Alex Deucher

drm/amd/display: Fix crash in hwss_set_output_transfer_func()

2026-08-06T17:46:24+00:00

The pipe_ctx->plane_res.hubp pointer is NULL on all DCE
hardware, which causes a kernel NULL pointer dereference
on all Vega and older GPUs.

Let's add a simple NULL check.

Fixes: 6bfca938471b ("drm/amd/display: Refactor DPP_SET_OUTPUT_TRANSFER_FUNC to drop pipe_ctx")
Signed-off-by: Timur Kristóf 
Cc: Tomasz Siemek 
Signed-off-by: Alex Deucher

drm/amd/display: Migrate color manager HW and fix MCM blend LUT issues

2026-08-06T16:44:26+00:00

Combine two related color manager improvements:

1. Migrate MCM/RMCM, shaper and 3DLUT HW programming to dc_plane_cm
   - Continue convergence with upstream Color Manager refactor
   - Migrate MCM/RMCM, shaper and 3DLUT programming for dcn401+ to dc_plane_cm
   - Unify MCM programming across both legacy and 3DLUT DMA paths
   - Add 3DLUT DMA broadcast support for multi-pipe planes

2. Reprogram MCM blend LUT on blend_enable falling edge
   - Fix issue where SDR desktop remained desaturated after video playback
   - Detect blend_enable falling edge (1->0) in surface update detection
   - Force MCM LUT reprogramming on blend state change

Reviewed-by: Dillon Varone 
Signed-off-by: Rafal Ostrowski 
Signed-off-by: Roman Li 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Enable DCN6 sources compilation

2026-08-06T13:53:32+00:00

- Add hooks in various entry points to perform hw/sw init for DCN6 asic
- Add dependent changes needed to enable DCN6 asic
- Update the Makefiles so that DCN6 related newly added sources are compiled

Signed-off-by: Aurabindo Pillai 
Signed-off-by: Roman Li 
Reviewed-by: Ivan Lipski 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add get replay residency function

2026-07-28T23:17:31+00:00

[Why&How]
Add dc interface to export link service function for getting Replay
residency

Reviewed-by: Robin Chen 
Signed-off-by: Huang, Leon 
Signed-off-by: Fangzhi Zuo 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Use current mpc pipe in set output transfer func

2026-07-28T23:17:30+00:00

[why]
Only the top pipe had the output transfer function programmed.

[how]
Program the current pipe from the MPC chain during fast sequence build.

Reviewed-by: Martin Leung 
Reviewed-by: Alvin Lee 
Signed-off-by: Tomasz Siemek 
Signed-off-by: Fangzhi Zuo 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix force FRL rate debug setting

2026-07-28T22:58:15+00:00

[Why & How]
- force FRL rate debug bit was not correctly forcing requested FRL rate

Reviewed-by: Chris Park 
Signed-off-by: Relja Vojvodic 
Signed-off-by: Fangzhi Zuo 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher