linux.git/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c, branch v7.2

drm/amd/display: Add IN_FORMATS_ASYNC support for planes

2026-06-17T22:16:57+00:00

[Why]
The DRM core exposes an IN_FORMATS_ASYNC plane property describing the
set of format/modifier pairs that are valid for asynchronous (immediate)
page flips. amdgpu already advertises async page flip support via
mode_config.async_page_flip = true, but never implemented the
.format_mod_supported_async plane callback, so the IN_FORMATS_ASYNC
property was not created.

This inconsistency (advertising async flips while exposing IN_FORMATS but
no IN_FORMATS_ASYNC) causes userspace, such as igt-gpu-tools, to emit a
repeated warning during plane initialization, which in turn demotes many
otherwise passing KMS subtests to a WARN result.

[How]
Wire up .format_mod_supported_async to the existing
amdgpu_dm_plane_format_mod_supported callback so the async format list is
populated. amdgpu does not restrict async flips at the format/modifier
level: the async flip constraints are enforced at atomic check and commit
time and only require a fast update (no change to FB pitch, DCC state,
rotation or memory type) between the old and new buffers. Therefore the
set of formats/modifiers valid for async flips is identical to the
regular IN_FORMATS set, and the same callback can be reused.

Reviewed-by: Aurabindo Pillai 
Signed-off-by: James Lin 
Signed-off-by: Ivan Lipski 
Signed-off-by: Alex Deucher 
(cherry picked from commit 8e2d7bbd6b184c0c1b0fe7cb404c9b5214d89931)

drm: Rename struct drm_atomic_state to drm_atomic_commit

2026-05-04T04:05:04+00:00

The KMS framework uses two slightly different definitions for the state
concept. For a given object (plane, CRTC, encoder, etc., so
drm_$OBJECT_state), the state is the entire state of that object.
However, at the device level, drm_atomic_state refers to a state update
for a limited number of objects.

Thus, drm_atomic_state isn't the entire device state, but only the full
state of some objects in that device. This has been an endless source of
confusion and thus bugs.

We can rename the drm_atomic_state structure to drm_atomic_commit to
make it less confusing.

This patch was created using:

rg -l drm_atomic_state | \
	xargs sed -i 's/drm_atomic_state/drm_atomic_commit/g; s/drm_atomic_commit_helper/drm_atomic_state_helper/g'
mv drivers/gpu/drm/tests/drm_atomic_state_test.c drivers/gpu/drm/tests/drm_atomic_commit_test.c

Acked-by: Simona Vetter 
Acked-by: Thomas Zimmermann 
Acked-by: Jani Nikula 
Reviewed-by: Luca Ceresoli 
Tested-by: Luca Ceresoli 
Signed-off-by: Maxime Ripard 
Signed-off-by: Dave Airlie 
Link: https://patch.msgid.link/20260427-drm-drm-atomic-update-v4-1-c0e713bfdf25@kernel.org

drm/amdgpu: use TTM_NUM_MOVE_FENCES when reserving fences

2026-03-30T19:16:33+00:00

Use TTM_NUM_MOVE_FENCES as an upperbound of how many fences
ttm might need to deal with moves/evictions.

Signed-off-by: Pierre-Eric Pelloux-Prayer 
Acked-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher

drm/amd/display: Add Idle state manager(ISM)

2026-03-30T19:14:05+00:00

[Why]

Rapid allow/disallow of idle optimization calls, whether it be IPS or
self-refresh features, can end up using more power if actual
time-in-idle is low. It can also spam DMUB command submission in a way
that prevents it from servicing other requestors.

[How]

Introduce the Idle State Manager (ISM) to amdgpu. It maintains a finite
state machine that uses a hysteresis to determine if a delay should be
inserted between a caller allowing idle, and when the actual idle
optimizations are programmed.

A second timer is also introduced to enable static screen optimizations
(SSO) such as PSR1 and Replay low HZ idle mode. Rapid SSO enable/disable
can have a negative power impact on some low hz video playback, and can
introduce user lag for PSR1 (due to up to 3 frames of sync latency).

This effectively rate-limits idle optimizations, based on hysteresis.

This also replaces the existing delay logic used for PSR1, allowing
drm_vblank_crtc_config.disable_immediate = true, and thus allowing
drm_crtc_vblank_restore().

v2:
* Loosen criteria for ISM to exit idle optimizations; it failed to exit
  idle correctly on cursor updates when there are no drm_vblank
  requestors,
* Document default_ism_config
* Convert pr_debug to trace events to reduce overhead on frequent
  codepaths
* checkpatch.pl fixes

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/4527
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3709
Fixes: 58a261bfc967 ("drm/amd/display: use a more lax vblank enable policy for older ASICs")
Signed-off-by: Ray Wu 
Signed-off-by: Leo Li 
Reviewed-by: Mario Limonciello (AMD) 
Signed-off-by: Alex Deucher

Revert "drm/amd/display: Add NV12/P010 formats to primary plane"

2026-03-17T21:48:34+00:00

With this change we're adding NV12 and P010 twice to reported
formats on a primary plane, which causes us to hit an assert
in Weston.

This reverts commit 63fff551318f5e0814b94f709a6dfaec789dcd7a.

Fixes: 63fff551318f ("drm/amd/display: Add NV12/P010 formats to primary plane")
Signed-off-by: Harry Wentland 
Reviewed-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: remove duplicate format modifier

2026-03-17T14:39:13+00:00

amdgpu_dm_plane_get_plane_modifiers always adds DRM_FORMAT_MOD_LINEAR to
the list of modifiers. However, with gfx12,
amdgpu_dm_plane_add_gfx12_modifiers also adds that modifier to the list.
So we end up with two copies. Most apps just ignore this but some
(Weston) don't like it.

As a fix, we change amdgpu_dm_plane_add_gfx12_modifiers to not add
DRM_FORMAT_MOD_LINEAR to the list, matching the behavior of analogous
functions for other chips.

Signed-off-by: Erik Kurzinger 
Acked-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amd/display: Add COLOR_ENCODING/COLOR_RANGE to overlay planes

2026-03-11T14:55:41+00:00

Extend COLOR_ENCODING and COLOR_RANGE property creation to overlay
planes in addition to primary planes. This allows overlay planes to
use YUV formats with proper color space configuration when the
hardware supports NV12/P010 formats.

These properties control the YUV-to-RGB conversion matrix selection
(BT.601/BT.709/BT.2020) and range handling (limited/full range).

Assisted-by: Claude: claude-sonnet-4.5
Reviewed-by: Alex Hung 
Signed-off-by: Harry Wentland 
Signed-off-by: Alex Hung 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add NV12/P010 formats to primary plane

2026-03-11T14:55:14+00:00

Add NV12, NV21, and P010 YUV formats to the primary plane's supported
format list, enabling YUV content to be scanned out directly from the
primary plane.

Assisted-by: Claude: claude-sonnet-4.5
Reviewed-by: Alex Hung 
Signed-off-by: Harry Wentland 
Signed-off-by: Alex Hung 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Enable DEGAMMA and reject COLOR_PIPELINE+DEGAMMA_LUT

2026-03-02T21:35:17+00:00

[WHAT]
Create DEGAMMA properties even if color pipeline is enabled, and enforce
the mutual exclusion in atomic check by rejecting any commit that
attempts to enable both COLOR_PIPELINE on the plane and DEGAMMA_LUT on
the CRTC simultaneously.

Fixes: 18a4127e9315 ("drm/amd/display: Disable CRTC degamma when color pipeline is enabled")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4963
Reviewed-by: Melissa Wen 
Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher

drm/amd/display: Enable dcn42 in DM

2026-02-23T19:28:33+00:00

Add support for DCN 4.2 in Display Manager

Signed-off-by: Roman Li 
Acked-by: Harry Wentland 
Signed-off-by: Alex Deucher