linux.git/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c, branch v5.6

drm/amd/display: Fix pageflip event race condition for DCN.

2020-03-19T20:18:45+00:00

Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
events at vsartup for DCN")' introduces a new way of pageflip
completion handling for DCN, and some trouble.

The current implementation introduces a race condition, which
can cause pageflip completion events to be sent out one vblank
too early, thereby confusing userspace and causing flicker:

prepare_flip_isr():

1. Pageflip programming takes the ddev->event_lock.
2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
3. Releases ddev->event_lock.

--> Deadline for surface address regs double-buffering passes on
    target pipe.

4. dc_commit_updates_for_stream() MMIO programs the new pageflip
   into hw, but too late for current vblank.

=> pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
   in current vblank due to missing the double-buffering deadline
   by a tiny bit.

5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
   dm_dcn_crtc_high_irq() gets called.

6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
   pageflip has been completed/will complete in this vblank and
   sends out pageflip completion event to userspace and resets
   pflip_status = AMDGPU_FLIP_NONE.

=> Flip completion event sent out one vblank too early.

This behaviour has been observed during my testing with measurement
hardware a couple of time.

The commit message says that the extra flip event code was added to
dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
in case the pflip irq doesn't fire, because the "DCH HUBP" component
is clock gated and doesn't fire pflip irqs in that state. Also that
this clock gating may happen if no planes are active. This suggests
that the problem addressed by that commit can't happen if planes
are active.

The proposed solution is therefore to only execute the extra pflip
completion code iff the count of active planes is zero and otherwise
leave pflip completion handling to the pflip irq handler, for a
more race-free experience.

Note that i don't know if this fixes the problem the original commit
tried to address, as i don't know what the test scenario was. It
does fix the observed too early pageflip events though and points
out the problem introduced.

Fixes: 16f17eda8bad ("drm/amd/display: Send vblank and user events at vsartup for DCN")
Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Mario Kleiner 
Signed-off-by: Alex Deucher

drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2)

2020-03-05T14:42:08+00:00

 This interface is for dGPU Navi1x. Linux dc-pplib interface depends
 on window driver dc implementation.

 For Navi1x, clock settings of dcn watermarks are fixed. the settings
 should be passed to smu during boot up and resume from s3.
 boot up: dc calculate dcn watermark clock settings within dc_create,
 dcn20_resource_construct, then call pplib functions below to pass
 the settings to smu:
 smu_set_watermarks_for_clock_ranges
 smu_set_watermarks_table
 navi10_set_watermarks_table
 smu_write_watermarks_table

 For Renoir, clock settings of dcn watermark are also fixed values.
 dc has implemented different flow for window driver:
 dc_hardware_init / dc_set_power_state
 dcn10_init_hw
 notify_wm_ranges
 set_wm_ranges

 For Linux
 smu_set_watermarks_for_clock_ranges
 renoir_set_watermarks_table
 smu_write_watermarks_table

 dc_hardware_init -> amdgpu_dm_init
 dc_set_power_state --> dm_resume

 therefore, linux dc-pplib interface of navi10/12/14 is different
 from that of Renoir.

v2: add missing unlock in error case

Signed-off-by: Hersen Wu 
Reviewed-by: Evan Quan 
Signed-off-by: Alex Deucher

drm/amdgpu/display: clean up hdcp workqueue handling

2020-02-19T16:03:24+00:00

Use the existence of the workqueue itself to determine when to
enable HDCP features rather than sprinkling asic checks all over
the code.  Also add a check for the existence of the hdcp
workqueue in the irq handling on the off chance we get and HPD
RX interrupt with the CP bit set.  This avoids a crash if
the driver doesn't support HDCP for a particular asic.

Fixes: 96a3b32e67236f ("drm/amd/display: only enable HDCP for DCN+")
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206519
Reviewed-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: Fix psr static frames calculation

2020-02-11T17:10:41+00:00

[Why]
Driver crash with psr feature enabled due to divide-by-zero error.
This is a regression after rework to calculate static screen frame
number entry time.

[How]
Correct order of operations to avoid divide-by-zero.

Signed-off-by: Roman Li 
Reviewed-by: Zhan Liu 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: Move drm_dp_mst_atomic_check() to the front of dc_validate_global_state()

2020-01-30T22:15:43+00:00

[Why]
Need to do atomic check first, then validate global state.
If not, when connecting both MST and HDMI displays and
set a bad mode via xrandr, system will hang.

[How]
Move drm_dp_mst_atomic_check() to the front of
dc_validate_global_state().

Signed-off-by: Zhan Liu 
Reviewed-by: Mikita Lipski 
Signed-off-by: Alex Deucher

drm/amd/display: Fix update type for multiple planes

2020-01-22T21:55:28+00:00

[Why]
determine_update_type_for_commit() uses pointers to single instance
of local variable to fill scaling/color info for all planes updates.
This is a bug, that leads to incorrect update type for commit in case
of multiple planes per crtc.
Each plane should refer to separate scaling/color data.

[How]
Use arrays for plane properties.
Bundle all properties into a single structure to simplify memory allocation.

Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: Do DMCUB hw_init before DC

2020-01-22T21:55:27+00:00

[Why]
For DMCUB enabled hardware DC has a dependency on DMCUB already being
running.

Command table offloading will fail on first modeset if DMCUB isn't
initialized first.

[How]
Perform DMCUB hardware initialization before DC.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Hersen Wu 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: make PSR static screen entry within 30 ms

2020-01-16T19:16:08+00:00

[Why]
With different refresh rate panels, the PSR entry/exit time is
different since it is dependent on 2 frame entry time today

[How]
Make static screen num frame entry time to be calculated
such that entry time is within 30 ms instead of fixed num
frames.

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Aric Cyr 
Acked-by: Harry Wentland 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amdgpu/display: set gpu vm flag for renoir

2020-01-14T15:18:10+00:00

It won't get used unless the driver allows the gtt domain for
display buffers which is controlled elsewhere.

Reviewed-by: Harry Wentland 
Acked-by: Huang Rui 
Acked-by: Christian König 
Signed-off-by: Alex Deucher

drm/amdgpu/display: set gpu vm flag for all asics which support it

2020-01-14T15:18:09+00:00

It won't get used unless the driver allows the gtt domain for
display buffers which is controlled elsewhere.

Acked-by: Huang Rui 
Acked-by: Christian König 
Reviewed-by: Harry Wentland 
Signed-off-by: Alex Deucher