<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/gpu/drm/amd/amdgpu/soc21.c, branch v6.1</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>drm/amdgpu: Enable gmc soft reset on gmc_v11_0_3</title>
<updated>2022-10-19T02:09:48+00:00</updated>
<author>
<name>YiPeng Chai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2022-09-27T05:16:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7cd3f6c3ace44ae9a9950a8c02ebcb8069278aab'/>
<id>7cd3f6c3ace44ae9a9950a8c02ebcb8069278aab</id>
<content type='text'>
Enable gmc soft reset on gmc_v11_0_3.

Signed-off-by: YiPeng Chai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable gmc soft reset on gmc_v11_0_3.

Signed-off-by: YiPeng Chai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: enable gfx clock gating features on smu_v13_0_10</title>
<updated>2022-10-19T02:09:23+00:00</updated>
<author>
<name>Kenneth Feng</name>
<email>kenneth.feng@amd.com</email>
</author>
<published>2022-09-07T09:05:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=657e07221ce046132dd78f6e19c04b32a78b1d25'/>
<id>657e07221ce046132dd78f6e19c04b32a78b1d25</id>
<content type='text'>
enable gfx clock gating features on smu_v13_0_10

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Reviewed-by: Jack Gui &lt;Jack.Gui@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
enable gfx clock gating features on smu_v13_0_10

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Reviewed-by: Jack Gui &lt;Jack.Gui@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable VCN PG on GC11_0_1</title>
<updated>2022-10-06T16:02:49+00:00</updated>
<author>
<name>Sonny Jiang</name>
<email>sonny.jiang@amd.com</email>
</author>
<published>2022-09-30T20:23:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e626d9b9c6e038a6918aad1b5affd38f6b9deaed'/>
<id>e626d9b9c6e038a6918aad1b5affd38f6b9deaed</id>
<content type='text'>
Enable VCN PG on GC11_0_1

Signed-off-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.0.x
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable VCN PG on GC11_0_1

Signed-off-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.0.x
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable VCN DPG for GC11_0_1</title>
<updated>2022-09-30T15:20:43+00:00</updated>
<author>
<name>Sonny Jiang</name>
<email>sonny.jiang@amd.com</email>
</author>
<published>2022-09-29T16:24:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0b37f47494099e74b3cc11d71a763b36b70ea2b7'/>
<id>0b37f47494099e74b3cc11d71a763b36b70ea2b7</id>
<content type='text'>
Enable VCN DPG on GC11_0_1

Signed-off-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable VCN DPG on GC11_0_1

Signed-off-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable full reset when RAS is supported on gc v11_0_0</title>
<updated>2022-09-13T16:56:16+00:00</updated>
<author>
<name>Candice Li</name>
<email>candice.li@amd.com</email>
</author>
<published>2022-09-07T07:58:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=34dfca890835ca9f4a59c8a2ff6be8c0513637c7'/>
<id>34dfca890835ca9f4a59c8a2ff6be8c0513637c7</id>
<content type='text'>
Enable full reset for RAS supported configuration on gc v11_0_0.

v2: simplify the code.

Signed-off-by: Candice Li &lt;candice.li@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable full reset for RAS supported configuration on gc v11_0_0.

v2: simplify the code.

Signed-off-by: Candice Li &lt;candice.li@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn: Disable CG/PG for SRIOV</title>
<updated>2022-09-01T19:12:00+00:00</updated>
<author>
<name>Jane Jian</name>
<email>Jane.Jian@amd.com</email>
</author>
<published>2022-08-22T07:15:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c322b422ab0f7b3b15c0cdd3f2c534094eaefcef'/>
<id>c322b422ab0f7b3b15c0cdd3f2c534094eaefcef</id>
<content type='text'>
For sriov, CG and MG are controlled from hypervisor side,
no need to manage them again in ip init

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Jane Jian &lt;Jane.Jian@amd.com&gt;
Reviewed-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For sriov, CG and MG are controlled from hypervisor side,
no need to manage them again in ip init

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Jane Jian &lt;Jane.Jian@amd.com&gt;
Reviewed-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/admgpu: Skip CG/PG on SOC21 under SRIOV VF</title>
<updated>2022-09-01T19:11:54+00:00</updated>
<author>
<name>Yifan Zha</name>
<email>Yifan.Zha@amd.com</email>
</author>
<published>2022-08-19T03:02:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=828418259254863e0af5805bd712284e2bd88e3b'/>
<id>828418259254863e0af5805bd712284e2bd88e3b</id>
<content type='text'>
[Why]
There is no CG(Clock Gating)/PG(Power Gating) requirement on SRIOV VF.
For multi VF, VF should not enable any CG/PG features.
For one VF, PF will program CG/PG related registers.

[How]
Do not set any cg/pg flag bit at early init under sriov.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Yifan Zha &lt;Yifan.Zha@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why]
There is no CG(Clock Gating)/PG(Power Gating) requirement on SRIOV VF.
For multi VF, VF should not enable any CG/PG features.
For one VF, PF will program CG/PG related registers.

[How]
Do not set any cg/pg flag bit at early init under sriov.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Yifan Zha &lt;Yifan.Zha@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu: Use RLCG to program GRBM_GFX_CNTL during full access time</title>
<updated>2022-09-01T19:11:50+00:00</updated>
<author>
<name>Yifan Zha</name>
<email>Yifan.Zha@amd.com</email>
</author>
<published>2022-08-17T09:25:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=bbb860d46fcbde5881c93ed549445a85f2434a64'/>
<id>bbb860d46fcbde5881c93ed549445a85f2434a64</id>
<content type='text'>
[Why]
KIQ register init requires GRBM_GFX_CNTL to select KIQ.

[How]
As RLCG accessing registers will save the data of GRBM_GFX_CNTL and restore it.
Use RLCG indirect accessing register method to select grbm instead of mmio directly access.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Yifan Zha &lt;Yifan.Zha@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why]
KIQ register init requires GRBM_GFX_CNTL to select KIQ.

[How]
As RLCG accessing registers will save the data of GRBM_GFX_CNTL and restore it.
Use RLCG indirect accessing register method to select grbm instead of mmio directly access.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Yifan Zha &lt;Yifan.Zha@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable pg/cg flags on GC11_0_3 for VCN</title>
<updated>2022-08-29T21:59:30+00:00</updated>
<author>
<name>Sonny Jiang</name>
<email>sonny.jiang@amd.com</email>
</author>
<published>2022-08-04T20:56:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0f05a2e52862107aff6f4ffe8e8926ada4432c9f'/>
<id>0f05a2e52862107aff6f4ffe8e8926ada4432c9f</id>
<content type='text'>
This enable VCN PG, CG, DPG and JPEG PG, CG

Signed-off-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: John Clements &lt;john.clements@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This enable VCN PG, CG, DPG and JPEG PG, CG

Signed-off-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: John Clements &lt;john.clements@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu: initialize common sw config for v11_0_3</title>
<updated>2022-08-29T21:59:30+00:00</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2022-06-27T16:41:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6b46251c5067990651bdbfc3edf07c2e16850a0c'/>
<id>6b46251c5067990651bdbfc3edf07c2e16850a0c</id>
<content type='text'>
init cp/pg_flags and extenal_rev_id

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Frank Min &lt;Frank.Min@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
init cp/pg_flags and extenal_rev_id

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Frank Min &lt;Frank.Min@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
