linux.git/drivers/gpu/drm/amd/amdgpu/soc15_common.h, branch v5.6

drm/amdgpu: Ensure ret is always initialized when using SOC15_WAIT_ON_RREG

2019-11-26T14:48:57+00:00

Commit b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from
VCN2.0") introduced a new clang warning in the vcn_v2_0_stop function:

../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: warning: variable 'r'
is used uninitialized whenever 'while' loop exits because its condition
is false [-Wsometimes-uninitialized]
        SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
expanded from macro 'SOC15_WAIT_ON_RREG'
                while ((tmp_ & (mask)) != (expected_value)) {   \
                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1083:6: note: uninitialized use
occurs here
        if (r)
            ^
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: note: remove the
condition if it is always true
        SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
        ^
../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
expanded from macro 'SOC15_WAIT_ON_RREG'
                while ((tmp_ & (mask)) != (expected_value)) {   \
                       ^
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1072:7: note: initialize the
variable 'r' to silence this warning
        int r;
             ^
              = 0
1 warning generated.

To prevent warnings like this from happening in the future, make the
SOC15_WAIT_ON_RREG macro initialize its ret variable before the while
loop that can time out. This macro's return value is always checked so
it should set ret in both the success and fail path.

Link: https://github.com/ClangBuiltLinux/linux/issues/776
Signed-off-by: Nathan Chancellor 
Signed-off-by: Alex Deucher

drm/amdgpu: cleanup vega10 SRIOV code path

2019-08-02T15:17:21+00:00

we can simplify all those unnecessary function under
SRIOV for vega10 since:
1) PSP L1 policy is by force enabled in SRIOV
2) original logic always set all flags which make itself
   a dummy step

besides,
1) the ih_doorbell_range set should also be skipped
for VEGA10 SRIOV.
2) the gfx_common registers should also be skipped
for VEGA10 SRIOV.

Signed-off-by: Monk Liu 
Reviewed-by: Emily Deng 
Signed-off-by: Alex Deucher

drm/amdgpu: move the VCN DPG mode read and write to VCN

2019-05-24T17:20:52+00:00

Since this is VCN specific and only used by VCN

Signed-off-by: Leo Liu 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu: add basic func for RLC program reg

2019-05-24T17:20:51+00:00

New feature for RLC, some registers can be programmed by
RLC interface under SR-IOV VF:

WREG32_SOC15_RLC_SHADOW:
	1, for GRBM_GFX_CNTL, firstly the new register value should be be
		programmed to SCRATCH_REG2
	1, for GRBM_GFX_INDEX, firstly the new register value should be be
		programmed to SCRATCH_REG3

WREG32_RLC:
	for registers supported to be programmed by RLC interface, the
	following sequence should be used:
		1, write the value to SCRATCH_REG0
		2, write reg | 0x80000000 to SCRATCH_REG1
		3, write 0x1 to RLC_SPARE_INT to notify RLC
		4, polling SCRATCH_REG1 to check if finished

Signed-off-by: Trigger Huang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREG

2018-12-18T22:39:03+00:00

If register value is updating, reset timeout counter.
It improves robustness of SOC15_WAIT_ON_RREG.

Signed-off-by: James Zhu 
Reviewed-by: Leo Liu 
Signed-off-by: Alex Deucher

drm/amdgpu/soc15: fix warnings in register macro

2018-09-27T02:09:26+00:00

expects argument of type ‘unsigned int’ has type ‘long int’

Fixes: 52e211c1f04 ("drm/amdgpu:Add error message when register failed to reach expected value")
Reviewed-by: Christian König 
Reviewed-by: James Zhu 
Signed-off-by: Alex Deucher

drm/amdgpu:Add DPG mode read/write macro

2018-09-27T02:09:24+00:00

Some registers read/write needs program through SDRAM pool under
DPG mode.

Signed-off-by: James Zhu 
Reviewed-by: Alex Deucher 
Reviewed-by: Huang Rui 
Acked-by: Christian König 
Signed-off-by: Alex Deucher

drm/amdgpu:Add error message when register failed to reach expected value

2018-09-13T20:14:08+00:00

Add error message when register failed to reach expected value, It will
help discover potential issue.

Signed-off-by: James Zhu 
Acked-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu: Add SOC15_WAIT_ON_RREG macro define

2018-05-24T05:18:02+00:00

Add new macro to wait on a register field to be a specific
value.

Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
Signed-off-by: Alex Deucher

drm/amdgpu: convert nbio to use callbacks (v2)

2017-12-13T22:28:07+00:00

Cleans up and consolidates all of the per-asic logic.

v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming)

Acked-by: Christian König 
Signed-off-by: Alex Deucher