linux.git/drivers/gpu/drm/amd/amdgpu/soc15.c, branch v4.12 Linux kernel source tree drm/amdgpu/soc15: use atomfirmware for setting bios scratch for reset 2017-05-10T15:23:28+00:00 Alex Deucher alexander.deucher@amd.com 2017-05-05T14:26:12+00:00 bfc181af3b3978e4b9619e3b46b1c4f7e5adb43a Need to use the atomfirmware interface rather than atombios since soc15 is atomfirmware based. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Need to use the atomfirmware interface rather than atombios since
soc15 is atomfirmware based.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/soc15: enable UVD code path for sriov 2017-04-28T21:33:01+00:00 Frank Min Frank.Min@amd.com 2017-04-17T03:19:45+00:00 91faed9ee150fb07b5b0e6601b96219a6c74301f Enable UVD block for SRIOV. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Enable UVD block for SRIOV.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu:invoke new implemented AI MB func 2017-04-06T17:28:07+00:00 Monk Liu Monk.Liu@amd.com 2017-04-05T05:04:50+00:00 81758c55956d91feae2f11e3dbf20b5ce45c6f23 Implement the sr-iov mailbox for soc15 asics. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Implement the sr-iov mailbox for soc15 asics.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu:add PSP block only load_type=PSP (v2) 2017-04-06T17:28:04+00:00 Monk Liu Monk.Liu@amd.com 2017-03-30T10:00:20+00:00 bb5c9ca588d1e7856f5c95250adb2c2d2617ccf9 SRIOV currently only can load ucode directly, and PSP block is not supported by VF temporarily. will remove this restrict and use PSP load all ucode even for SRIOV later v2: squash in check against module parameter Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
SRIOV currently only can load ucode directly, and PSP
block is not supported by VF temporarily.

will remove this restrict and use PSP load all ucode
even for SRIOV later

v2: squash in check against module parameter

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/soc15: Fix static checker warnings 2017-04-05T03:33:26+00:00 Alex Deucher alexander.deucher@amd.com 2017-04-03T20:56:08+00:00 1fdc639b7a2bd28067e449436305bc535345f6fc vega10 is the only soc15 asic at the moment so these warnings are invalid, but add a default case to silence the warnings. Fixes: 220ab9bd1ccf: "drm/amdgpu: soc15 enable (v3)" Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
vega10 is the only soc15 asic at the moment so these
warnings are invalid, but add a default case to silence
the warnings.

Fixes: 220ab9bd1ccf: "drm/amdgpu: soc15 enable (v3)"
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: remove duplicate allowed reg CP_CPF_BUSY_STAT 2017-03-30T18:43:59+00:00 Christian König christian.koenig@amd.com 2017-03-24T13:05:37+00:00 bcf32a2371017c5de92cf9d36c811dc26076898a Remove duplicate mmCP_CPF_BUSY_STAT from the allowed registers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Remove duplicate mmCP_CPF_BUSY_STAT from the allowed registers.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/soc15: enable psp block for SRIOV 2017-03-30T03:55:55+00:00 Xiangliang Yu Xiangliang.Yu@amd.com 2017-03-28T11:16:42+00:00 c6f3e7cb13bb9e9b1760f0dda37b96a6d1c6ef28 SRIOV can support for loading ucode with PSP block, enable it. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
SRIOV can support for loading ucode with PSP block, enable it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/soc15: bypass pp block for vf 2017-03-30T03:55:55+00:00 Xiangliang Yu Xiangliang.Yu@amd.com 2017-02-28T09:26:40+00:00 cfd8373320565fbe83d936e616811bb195b3bc52 Disable pp block if device is vf. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Disable pp block if device is  vf.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/soc15: drop support for reading some registers 2017-03-30T03:55:46+00:00 Alex Deucher alexander.deucher@amd.com 2017-03-27T18:40:36+00:00 480e9150ea329fc774f943a56c8de9cc361efef1 The RB harvest registers are not necessary, the driver already exposes this info via the info ioctl. GB_BACKEND_MAP has been deprecated since SI and is not relevant to the RB mapping. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
The RB harvest registers are not necessary, the driver already
exposes this info via the info ioctl.  GB_BACKEND_MAP has
been deprecated since SI and is not relevant to the RB mapping.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/soc15: return cached values for some registers (v2) 2017-03-30T03:55:45+00:00 Alex Deucher alexander.deucher@amd.com 2017-03-24T19:05:07+00:00 c013cea2df9c06aca7e218d8d41693ba2d17455d Required for SR-IOV and saves MMIO transactions. v2: drop cached RB harvest registers Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Required for SR-IOV and saves MMIO transactions.

v2: drop cached RB harvest registers

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>