linux.git/drivers/edac, branch v4.8-rc2

Merge tag 'edac_for_4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

2016-07-27T20:40:47+00:00

Pull EDAC updates from Borislav Petkov:
 "This last cycle, Thor was busy adding Arria10 eth FIFO support to the
  altera_edac driver along with other improvements.  We have two
  cleanups/fixes too.

  Summary:

   - Altera Arria10 ethernet FIFO buffer support (Thor Thayer)

   - Minor cleanups"

* tag 'edac_for_4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  ARM: dts: Add Arria10 Ethernet EDAC devicetree entry
  EDAC, altera: Add Arria10 Ethernet EDAC support
  EDAC, altera: Add Arria10 ECC memory init functions
  Documentation: dt: socfpga: Add Arria10 Ethernet binding
  EDAC, altera: Drop some ifdeffery
  EDAC, altera: Add panic flag check to A10 IRQ
  EDAC, altera: Check parent status for Arria10 EDAC block
  EDAC, altera: Make all private data structures static
  EDAC: Correct channel count limit
  EDAC, amd64_edac: Init opstate at the proper time during init
  EDAC, altera: Handle Arria10 SDRAM child node
  EDAC, altera: Add ECC Manager IRQ controller support
  Documentation: dt: socfpga: Add interrupt-controller to ecc-manager

EDAC, sb_edac: Fix Knights Landing

2016-07-15T21:11:59+00:00

In commit 2c1ea4c700af ("EDAC, sb_edac: Use cpu family/model in driver
detection") I broke Knights Landing because I failed to notice that it
called a wrapper macro "sbridge_get_all_devices_knl" instead of
"sbridge_get_all_devices" like all the other types.

Now that we include the processor type in the pci_id_table structure we
can skip the wrappers and just have the sbridge_get_all_devices() check
the type to decide whether to allow duplicate devices and controllers to
have registers spread across buses.

Fixes: 2c1ea4c700af ("EDAC, sb_edac: Use cpu family/model in driver detection")
Tested-by: Lukasz Odzioba 
Acked-by: Aristeu Rozanski 
Signed-off-by: Tony Luck 
Signed-off-by: Linus Torvalds

EDAC, altera: Add Arria10 Ethernet EDAC support

2016-06-25T09:31:34+00:00

Add Altera Arria10 Ethernet FIFO memory EDAC support. Update to support
a common compatibility string for all Ethernet FIFOs in the DT.

Signed-off-by: Thor Thayer 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac 
Link: http://lkml.kernel.org/r/1466603939-7526-8-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov

EDAC, altera: Add Arria10 ECC memory init functions

2016-06-24T19:16:38+00:00

In preparation for additional memory module ECCs, add the memory
initialization functions and helpers.

Signed-off-by: Thor Thayer 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac 
Link: http://lkml.kernel.org/r/1466603939-7526-7-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov

EDAC, altera: Drop some ifdeffery

2016-06-24T12:18:33+00:00

Make the IRQ and check_deps() functions available to all the memory
buffers by moving them outside of the OCRAM only area.

Signed-off-by: Thor Thayer 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac 
Link: http://lkml.kernel.org/r/1466603939-7526-5-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov

EDAC, altera: Add panic flag check to A10 IRQ

2016-06-24T09:58:43+00:00

In preparation for additional memory module ECCs, the IRQ function will
check a panic flag before doing a kernel panic on double bit errors.

OCRAM uncorrectable errors cause a panic because sleep/resume functions
and FPGA contents during sleep are stored in OCRAM.

ECCs on peripheral FIFO buffers will not cause a kernel panic on DBERRs
because the packet can be retried and therefore recovered.

Signed-off-by: Thor Thayer 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac 
Link: http://lkml.kernel.org/r/1466603939-7526-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov

EDAC, altera: Check parent status for Arria10 EDAC block

2016-06-24T09:58:42+00:00

In preparation for the Arria10 ECC modules, check the status of the
parent in the device tree to ensure the block is enabled. Skip if no
parent phandle is set in the device tree.

Signed-off-by: Thor Thayer 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac 
Link: http://lkml.kernel.org/r/1466603939-7526-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov

EDAC, altera: Make all private data structures static

2016-06-24T09:58:42+00:00

The device private data structures are used only here so make them
static.

Signed-off-by: Thor Thayer 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac 
Link: http://lkml.kernel.org/r/1466603939-7526-4-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov

EDAC: Correct channel count limit

2016-06-16T08:06:35+00:00

c44696fff04f ("EDAC: Remove arbitrary limit on number of channels")
lifted the arbitrary limit on memory controller channels in EDAC.
However, the dynamic channel attributes dynamic_csrow_dimm_attr and
dynamic_csrow_ce_count_attr remained 6.

This wasn't a problem except channels 6 and 7 weren't visible in sysfs
on machines with more than 6 channels after the conversion to static
attr groups with

  2c1946b6d629 ("EDAC: Use static attribute groups for managing sysfs entries")

 [ without that, we're exploding in edac_create_sysfs_mci_device()
   because we're dereferencing out of the bounds of the
   dynamic_csrow_dimm_attr array. ]

Add attributes for channels 6 and 7 along with a guard for the
future, should more channels be required and/or to sanity check for
misconfigured machines.

We still need to check against the number of channels present on the MC
first, as Thor reported.

Signed-off-by: Borislav Petkov 
Reported-by: Hironobu Ishii 
Tested-by: Thor Thayer 
Cc:  # 4.2

EDAC, amd64_edac: Init opstate at the proper time during init

2016-06-15T23:13:18+00:00

It is useless to do it if we're loaded on unsupported hardware so do
that only after we have detected at least 1 supported AMD northbridge.

Signed-off-by: Borislav Petkov