linux.git/drivers/dma/stm32, branch for-next

dmaengine: stm32-dma3: clamp AXI burst using match data

2024-10-21T17:21:45+00:00

STM32 DMA3 can be interconnected with AXI3 or AXI4 busses. In case it is
interconnected with AXI3, the maximum burst length supported by AXI3
protocol is 16 beats, which is lower than the maximum burst length
supported by STM32 DMA3. So the programmed burst has to be shortened when
AXI port is used.
Introduce struct stm32_dma3_pdata to specify the specific configurations
(e.g. AXI maximum burst length) required by the SoC, so implied by the SoC
specific compatible.

Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-6-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul

dmaengine: stm32-dma3: prevent LL refactoring thanks to DT configuration

2024-10-21T17:21:45+00:00

stm32-dma3 driver refactors the linked-list in order to address the memory
with the highest possible data width.
It means that it can introduce up to 2 linked-list items. One with a
transfer length multiple of channel maximum burst length and so with the
highest possible data width. And an extra one with the latest bytes, with
lower data width.
Some devices (e.g. FMC ECC) don't support having several transfers instead
of only one.
So add the possibility to prevent linked-list refactoring, when bit 17 of
the 'DMA transfer requirements' bit mask is set in device tree.
When NOPACK feature is used (bit 16 pf the 'DMA transfer requirements' bit
mask in device tree), linked-list refactoring can be avoided, since the
memory data width and burst will be aligned with the device ones.

Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-5-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul

dmaengine: stm32-dma3: refactor HW linked-list to optimize memory accesses

2024-10-21T17:21:45+00:00

Current behavior splits the buffer/sg in n * STM32_DMA3_MAX_BLOCK_SIZE + 1
for the remainder without optimization.

New behavior splits the buffer/sg in n * STM32_DMA3_MAX_BLOCK_SIZE + 1 for
(x * chan->max_burst) + 1 for the remainder.
Depending on channel FIFO size, optimal double-word (word if only 8-byte
FIFO size) bursts can be programmed before managing the very last remainder
with lower data width.
In case of _prep_slave_sg, and depending on the channel Transfer Complete
event configuration, the user is warned about the refactored linked-list,
not having the same items count than the initial sg_list. This warning is
shown only if the configuration is successful.

Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-3-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul

dmaengine: stm32-dma3: prevent pack/unpack thanks to DT configuration

2024-10-21T17:21:44+00:00

When source data width/burst and destination data width/burst are
different, data are packed or unpacked in DMA3 channel FIFO, using
CxTR1.PAM.
Data are pushed out from DMA3 channel FIFO when the destination burst
length (= data width * burst) is reached.
If the transfer is stopped before CxBR1.BNDT = 0, and if some bytes are
packed/unpacked in the DMA3 channel FIFO, these bytes are lost.
Indeed, DMA3 channel FIFO has no flush capability, only reset.
To avoid potential bytes lost, pack/unpack must be prevented by setting
memory data width/burst equal to peripheral data width/burst.
Memory accesses will be penalized. But it is the only way to avoid bytes
lost.

Prevent pack/unpack feature can be activated by setting bit 16 of DMA3
Transfer requirements bitfield (tr_conf) in device tree.

Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-2-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul

dmaengine: Switch back to struct platform_driver::remove()

2024-10-14T18:20:34+00:00

After commit 0edb555a65d1 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.

Convert all platform drivers below drivers/dma after the previous
conversion commits apart from the wireless drivers to use .remove(),
with the eventual goal to drop struct platform_driver::remove_new(). As
.remove() and .remove_new() have the same prototypes, conversion is done
by just changing the structure member name in the driver initializer.

Signed-off-by: Uwe Kleine-König 
Link: https://lore.kernel.org/r/20241004062227.187726-2-u.kleine-koenig@baylibre.com
Signed-off-by: Vinod Koul

dmaengine: stm32-dma3: Set lli_size after allocation

2024-08-05T16:58:48+00:00

With the new __counted_by annotation, the "lli_size" variable needs to
valid for accesses to the "lli" array. This requirement is not met in
stm32_dma3_chan_desc_alloc(), since "lli_size" starts at "0", so "lli"
index "0" will not be considered valid during the initialization for loop.

Fix this by setting lli_size immediately after allocation (similar to
how this is handled in stm32_mdma_alloc_desc() for the node/count
relationship).

Fixes: f561ec8b2b33 ("dmaengine: Add STM32 DMA3 support")
Signed-off-by: Kees Cook 
Reviewed-by: Gustavo A. R. Silva 
Link: https://lore.kernel.org/r/20240716213830.work.951-kees@kernel.org
Signed-off-by: Vinod Koul

dmaengine: stm32-dma3: defer channel registration to specify channel name

2024-06-11T18:25:34+00:00

On STM32 DMA3, channels can be reserved, so they are non available for
Linux. This non-availability creates a mismatch between dma_chan id and
DMA3 channel id.

Use dma_async_device_channel_register() to register the channels
after controller registration and change the default channel name, so that
it can match the name in the Reference Manual and ease requesting a channel
thanks to its name.

Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20240531150712.2503554-12-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul

dmaengine: stm32-dma3: improve residue granularity

2024-06-11T18:25:34+00:00

Implement own device_tx_status ops to compute the residue with a finer
granularity, up to bytes.
STM32 DMA3 has a bitfield, BNDT, in CxTR1 register which reflects the
number of bytes read from the source.
It also has a bitfield, FIFOL, in CxSR register which reflects the FIFO
level in units of programmed destination data width.
The channel is briefly suspended to get a coherent snapshot of registers.
It is possible to correct the fifo level when packing/unpacking is enabled
with destination increment.

Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20240531150712.2503554-10-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul

dmaengine: stm32-dma3: add device_pause and device_resume ops

2024-06-11T18:25:34+00:00

STM32 DMA3 controller is able to suspend an ongoing transfer (the transfer
is suspended after the ongoing burst is flushed to the destination) and
resume it from the point it was suspended. No need to reconfigure any
register.

Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20240531150712.2503554-9-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul

dmaengine: stm32-dma3: add DMA_MEMCPY capability

2024-06-11T18:25:34+00:00

Add DMA_MEMCPY capability and relative device_prep_dma_memcpy ops with
stm32_dma3_prep_dma_memcpy(). It reuses stm32_dma3_chan_prep_hw() and
stm32_dma3_prep_hwdesc() helpers.
As this driver relies on both device_config and of_xlate ops to
pre-configure the channel for transfer, add a new helper
(stm32_dma3_init_chan_config_for_memcpy) in case the channel is used
without being pre-configured (with DT and/or dmaengine_slave_config()).

Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20240531150712.2503554-8-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul