<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/cpufreq, branch v5.18-rc2</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>Merge branch 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm</title>
<updated>2022-03-22T11:15:47+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2022-03-22T11:15:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2353828f3695ecbbc3fb4b695fa6c77323db42d0'/>
<id>2353828f3695ecbbc3fb4b695fa6c77323db42d0</id>
<content type='text'>
Pull ARM cpufreq updates for 5.18-rc1 fron Viresh Kumar:

"- Add per core DVFS support for QCom SoC (Bjorn Andersson), convert to yaml
   binding (Manivannan Sadhasivam) and various other fixes to the QCom drivers
   (Luca Weiss).

 - Add OPP table for imx7s SoC (Denys Drozdov) and minor fixes (Stefan Agner).

 - Fix CPPC driver's freq/performance conversions (Pierre Gondois).

 - Minor generic cleanups (Yury Norov)."

* 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
  dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings
  dt-bindings: dvfs: Use MediaTek CPUFREQ HW as an example
  cpufreq: blocklist Qualcomm sc8280xp and sa8540p in cpufreq-dt-platdev
  cpufreq: qcom-hw: Add support for per-core-dcvs
  cpufreq: CPPC: Fix performance/frequency conversion
  cpufreq: Add i.MX7S to cpufreq-dt-platdev blocklist
  ARM: dts: imx7s: Define operating points table for cpufreq
  cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuse
  cpufreq: replace cpumask_weight with cpumask_empty where appropriate
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull ARM cpufreq updates for 5.18-rc1 fron Viresh Kumar:

"- Add per core DVFS support for QCom SoC (Bjorn Andersson), convert to yaml
   binding (Manivannan Sadhasivam) and various other fixes to the QCom drivers
   (Luca Weiss).

 - Add OPP table for imx7s SoC (Denys Drozdov) and minor fixes (Stefan Agner).

 - Fix CPPC driver's freq/performance conversions (Pierre Gondois).

 - Minor generic cleanups (Yury Norov)."

* 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
  dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings
  dt-bindings: dvfs: Use MediaTek CPUFREQ HW as an example
  cpufreq: blocklist Qualcomm sc8280xp and sa8540p in cpufreq-dt-platdev
  cpufreq: qcom-hw: Add support for per-core-dcvs
  cpufreq: CPPC: Fix performance/frequency conversion
  cpufreq: Add i.MX7S to cpufreq-dt-platdev blocklist
  ARM: dts: imx7s: Define operating points table for cpufreq
  cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuse
  cpufreq: replace cpumask_weight with cpumask_empty where appropriate
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'pm-tools'</title>
<updated>2022-03-18T17:46:15+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2022-03-18T17:46:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ec3d8b8365e9865b43099e943ec5f0bc12f28f96'/>
<id>ec3d8b8365e9865b43099e943ec5f0bc12f28f96</id>
<content type='text'>
Merge power management utilities changes for 5.18-rc1:

 - Add tracer tool for the amd-pstate driver (Jinzhou Su).

 - Fix PC6 displaying in turbostat on some systems (Artem Bityutskiy).

 - Add AMD P-State support to the cpupower utility (Huang Rui).

* pm-tools:
  Documentation: amd-pstate: add tracer tool introduction
  tools/power/x86/amd_pstate_tracer: Add tracer tool for AMD P-state
  tools/power/x86/intel_pstate_tracer: make tracer as a module
  cpufreq: amd-pstate: Add more tracepoint for AMD P-State module
  turbostat: fix PC6 displaying on some systems
  cpupower: Add "perf" option to print AMD P-State information
  cpupower: Add function to print AMD P-State performance capabilities
  cpupower: Move print_speed function into misc helper
  cpupower: Enable boost state support for AMD P-State module
  cpupower: Add AMD P-State sysfs definition and access helper
  cpupower: Introduce ACPI CPPC library
  cpupower: Add the function to get the sysfs value from specific table
  cpupower: Initial AMD P-State capability
  cpupower: Add the function to check AMD P-State enabled
  cpupower: Add AMD P-State capability flag
  tools/power/cpupower/{ToDo =&gt; TODO}: Rename the todo file
  tools: cpupower: fix typo in cpupower-idle-set(1) manpage
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Merge power management utilities changes for 5.18-rc1:

 - Add tracer tool for the amd-pstate driver (Jinzhou Su).

 - Fix PC6 displaying in turbostat on some systems (Artem Bityutskiy).

 - Add AMD P-State support to the cpupower utility (Huang Rui).

* pm-tools:
  Documentation: amd-pstate: add tracer tool introduction
  tools/power/x86/amd_pstate_tracer: Add tracer tool for AMD P-state
  tools/power/x86/intel_pstate_tracer: make tracer as a module
  cpufreq: amd-pstate: Add more tracepoint for AMD P-State module
  turbostat: fix PC6 displaying on some systems
  cpupower: Add "perf" option to print AMD P-State information
  cpupower: Add function to print AMD P-State performance capabilities
  cpupower: Move print_speed function into misc helper
  cpupower: Enable boost state support for AMD P-State module
  cpupower: Add AMD P-State sysfs definition and access helper
  cpupower: Introduce ACPI CPPC library
  cpupower: Add the function to get the sysfs value from specific table
  cpupower: Initial AMD P-State capability
  cpupower: Add the function to check AMD P-State enabled
  cpupower: Add AMD P-State capability flag
  tools/power/cpupower/{ToDo =&gt; TODO}: Rename the todo file
  tools: cpupower: fix typo in cpupower-idle-set(1) manpage
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: powernow-k8: Re-order the init checks</title>
<updated>2022-03-17T13:54:11+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2022-03-16T21:55:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3870a44d50feeb5118a2698617d251123d9cde4c'/>
<id>3870a44d50feeb5118a2698617d251123d9cde4c</id>
<content type='text'>
The powernow-k8 driver will do checks at startup that the current
active driver is acpi-cpufreq and show a warning when they're not
expected.

Because of this the following warning comes up on systems that
support amd-pstate and compiled in both drivers:
`WTF driver: amd-pstate`

The systems that support powernow-k8 will not support amd-pstate,
so re-order the checks to validate the CPU model number first to
avoid this warning being displayed on modern SOCs.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The powernow-k8 driver will do checks at startup that the current
active driver is acpi-cpufreq and show a warning when they're not
expected.

Because of this the following warning comes up on systems that
support amd-pstate and compiled in both drivers:
`WTF driver: amd-pstate`

The systems that support powernow-k8 will not support amd-pstate,
so re-order the checks to validate the CPU model number first to
avoid this warning being displayed on modern SOCs.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Use firmware default EPP</title>
<updated>2022-03-16T18:14:55+00:00</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2022-03-10T22:42:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3d13058ed2a6d0ddb55a45a979acc49a845be874'/>
<id>3d13058ed2a6d0ddb55a45a979acc49a845be874</id>
<content type='text'>
For some specific platforms (E.g. AlderLake) the balance performance
EPP is updated from the hard coded value in the driver. This acts as
the default and balance_performance EPP. The purpose of this EPP
update is to reach maximum 1 core turbo frequency (when possible) out
of the box.

Although we can achieve the objective by using hard coded value in the
driver, there can be other EPP which can be better in terms of power.
But that will be very subjective based on platform and use cases.
This is not practical to have a per platform specific default hard coded
in the driver.

If a platform wants to specify default EPP, it can be set in the firmware.
If this EPP is not the chipset default of 0x80 (balance_perf_epp unless
driver changed it) and more performance oriented but not 0, the driver
can use this as the default and balanced_perf EPP. In this case no driver
update is required every time there is some new platform and default EPP.

If the firmware didn't update the EPP from the chipset default then
the hard coded value is used as per existing implementation.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For some specific platforms (E.g. AlderLake) the balance performance
EPP is updated from the hard coded value in the driver. This acts as
the default and balance_performance EPP. The purpose of this EPP
update is to reach maximum 1 core turbo frequency (when possible) out
of the box.

Although we can achieve the objective by using hard coded value in the
driver, there can be other EPP which can be better in terms of power.
But that will be very subjective based on platform and use cases.
This is not practical to have a per platform specific default hard coded
in the driver.

If a platform wants to specify default EPP, it can be set in the firmware.
If this EPP is not the chipset default of 0x80 (balance_perf_epp unless
driver changed it) and more performance oriented but not 0, the driver
can use this as the default and balanced_perf EPP. In this case no driver
update is required every time there is some new platform and default EPP.

If the firmware didn't update the EPP from the chipset default then
the hard coded value is used as per existing implementation.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: unify show() and store() naming and use __ATTR_XX</title>
<updated>2022-03-10T18:55:05+00:00</updated>
<author>
<name>Lianjie Zhang</name>
<email>zhanglianjie@uniontech.com</email>
</author>
<published>2022-03-10T14:38:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=85750bcd480c74b13661ee2c9db49de500fd2823'/>
<id>85750bcd480c74b13661ee2c9db49de500fd2823</id>
<content type='text'>
Usually, sysfs attributes have .show and .store and their naming
convention is filename_show() and filename_store().

But in cpufreq the naming convention of these functions is
show_filename() and store_filename() which prevents __ATTR_RW() and
__ATTR_RO() from being used in there to simplify code.

Accordingly, change the naming convention of the sysfs .show and
.store methods in cpufreq to follow the one expected by __ATTR_RW()
and __ATTR_RO() and use these macros in that code.

Signed-off-by: Lianjie Zhang &lt;zhanglianjie@uniontech.com&gt;
[ rjw: Subject and changelog edits ]
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Usually, sysfs attributes have .show and .store and their naming
convention is filename_show() and filename_store().

But in cpufreq the naming convention of these functions is
show_filename() and store_filename() which prevents __ATTR_RW() and
__ATTR_RO() from being used in there to simplify code.

Accordingly, change the naming convention of the sysfs .show and
.store methods in cpufreq to follow the one expected by __ATTR_RW()
and __ATTR_RO() and use these macros in that code.

Signed-off-by: Lianjie Zhang &lt;zhanglianjie@uniontech.com&gt;
[ rjw: Subject and changelog edits ]
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: amd-pstate: Add more tracepoint for AMD P-State module</title>
<updated>2022-03-09T18:53:01+00:00</updated>
<author>
<name>Jinzhou Su</name>
<email>Jinzhou.Su@amd.com</email>
</author>
<published>2022-03-09T01:23:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=23c296fb7eeea99dec035521c07ae54c28b8a267'/>
<id>23c296fb7eeea99dec035521c07ae54c28b8a267</id>
<content type='text'>
Add frequency, mperf, aperf and tsc in the trace. This can be used
to debug and tune the performance of AMD P-state driver.

Use the time difference between amd_pstate_update to calculate CPU
frequency. There could be sleep in arch_freq_get_on_cpu, so do not
use it here.

Signed-off-by: Jinzhou Su &lt;Jinzhou.Su@amd.com&gt;
Co-developed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add frequency, mperf, aperf and tsc in the trace. This can be used
to debug and tune the performance of AMD P-state driver.

Use the time difference between amd_pstate_update to calculate CPU
frequency. There could be sleep in arch_freq_get_on_cpu, so do not
use it here.

Signed-off-by: Jinzhou Su &lt;Jinzhou.Su@amd.com&gt;
Co-developed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge back cpufreq changes for v5.18.</title>
<updated>2022-02-28T19:47:57+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2022-02-28T19:47:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=075c3c483c86aaeadbfdb56ff0ffa67abe582eca'/>
<id>075c3c483c86aaeadbfdb56ff0ffa67abe582eca</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: blocklist Qualcomm sc8280xp and sa8540p in cpufreq-dt-platdev</title>
<updated>2022-02-25T04:39:05+00:00</updated>
<author>
<name>Bjorn Andersson</name>
<email>bjorn.andersson@linaro.org</email>
</author>
<published>2022-02-25T03:57:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=72951a77c00fb23275c8164aeee409c06b6f197c'/>
<id>72951a77c00fb23275c8164aeee409c06b6f197c</id>
<content type='text'>
The Qualcomm sc8280xp and sa8540p platforms also uses the
qcom-cpufreq-hw driver, so add them to the cpufreq-dt-platdev driver's
blocklist.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The Qualcomm sc8280xp and sa8540p platforms also uses the
qcom-cpufreq-hw driver, so add them to the cpufreq-dt-platdev driver's
blocklist.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: qcom-hw: Add support for per-core-dcvs</title>
<updated>2022-02-24T04:27:55+00:00</updated>
<author>
<name>Bjorn Andersson</name>
<email>bjorn.andersson@linaro.org</email>
</author>
<published>2022-02-10T05:01:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c377d4ba86e9136b4923124ac1ed858d77020aaf'/>
<id>c377d4ba86e9136b4923124ac1ed858d77020aaf</id>
<content type='text'>
The OSM and EPSS hardware controls the frequency of each cluster in the
system based on requests from the OS and various limiting factors, such
as input from LMH.

In most systems the vote from the OS is done using a single register per
cluster, but some systems are configured to instead take one request per
core.  In this configuration a set of consecutive registers are used for
the OS to request the frequency of each of the cores within the cluster.
The information is then aggregated in the hardware and the frequency for
the cluster is determined.

As the current implementation ends up only requesting a frequency for
the first core in each cluster and only the vote of non-idle cores are
considered it's often the case that the cluster will be clocked (much)
lower than expected.

It's possible that there are benefits of performing the per-core
requests from the OS, but more investigation of the outcome is needed
before introducing such support. As such this patch extends the request
for the cluster to be written to all the cores.

The weight of the policy's related_cpus is used to determine how many
cores, and hence consecutive registers, each cluster has.

The OS is not permitted to disable the per-core dcvs feature.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The OSM and EPSS hardware controls the frequency of each cluster in the
system based on requests from the OS and various limiting factors, such
as input from LMH.

In most systems the vote from the OS is done using a single register per
cluster, but some systems are configured to instead take one request per
core.  In this configuration a set of consecutive registers are used for
the OS to request the frequency of each of the cores within the cluster.
The information is then aggregated in the hardware and the frequency for
the cluster is determined.

As the current implementation ends up only requesting a frequency for
the first core in each cluster and only the vote of non-idle cores are
considered it's often the case that the cluster will be clocked (much)
lower than expected.

It's possible that there are benefits of performing the per-core
requests from the OS, but more investigation of the outcome is needed
before introducing such support. As such this patch extends the request
for the cluster to be written to all the cores.

The weight of the policy's related_cpus is used to determine how many
cores, and hence consecutive registers, each cluster has.

The OS is not permitted to disable the per-core dcvs feature.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: CPPC: Fix performance/frequency conversion</title>
<updated>2022-02-10T05:26:52+00:00</updated>
<author>
<name>Pierre Gondois</name>
<email>Pierre.Gondois@arm.com</email>
</author>
<published>2022-02-08T08:01:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ec1c7ad47664f964c1101fe555b6fde0cb124b38'/>
<id>ec1c7ad47664f964c1101fe555b6fde0cb124b38</id>
<content type='text'>
CPUfreq governors request CPU frequencies using information
on current CPU usage. The CPPC driver converts them to
performance requests. Frequency targets are computed as:
	target_freq = (util / cpu_capacity) * max_freq
target_freq is then clamped between [policy-&gt;min, policy-&gt;max].

The CPPC driver converts performance values to frequencies
(and vice-versa) using cppc_cpufreq_perf_to_khz() and
cppc_cpufreq_khz_to_perf(). These functions both use two different
factors depending on the range of the input value. For
cppc_cpufreq_khz_to_perf():
- (NOMINAL_PERF / NOMINAL_FREQ) or
- (LOWEST_PERF / LOWEST_FREQ)
and for cppc_cpufreq_perf_to_khz():
- (NOMINAL_FREQ / NOMINAL_PERF) or
- ((NOMINAL_PERF - LOWEST_FREQ) / (NOMINAL_PERF - LOWEST_PERF))

This means:
1- the functions are not inverse for some values:
   (perf_to_khz(khz_to_perf(x)) != x)
2- cppc_cpufreq_perf_to_khz(LOWEST_PERF) can sometimes give
   a different value from LOWEST_FREQ due to integer approximation
3- it is implied that performance and frequency are proportional
   (NOMINAL_FREQ / NOMINAL_PERF) == (LOWEST_PERF / LOWEST_FREQ)

This patch changes the conversion functions to an affine function.
This fixes the 3 points above.

Suggested-by: Lukasz Luba &lt;lukasz.luba@arm.com&gt;
Suggested-by: Morten Rasmussen &lt;morten.rasmussen@arm.com&gt;
Signed-off-by: Pierre Gondois &lt;Pierre.Gondois@arm.com&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
CPUfreq governors request CPU frequencies using information
on current CPU usage. The CPPC driver converts them to
performance requests. Frequency targets are computed as:
	target_freq = (util / cpu_capacity) * max_freq
target_freq is then clamped between [policy-&gt;min, policy-&gt;max].

The CPPC driver converts performance values to frequencies
(and vice-versa) using cppc_cpufreq_perf_to_khz() and
cppc_cpufreq_khz_to_perf(). These functions both use two different
factors depending on the range of the input value. For
cppc_cpufreq_khz_to_perf():
- (NOMINAL_PERF / NOMINAL_FREQ) or
- (LOWEST_PERF / LOWEST_FREQ)
and for cppc_cpufreq_perf_to_khz():
- (NOMINAL_FREQ / NOMINAL_PERF) or
- ((NOMINAL_PERF - LOWEST_FREQ) / (NOMINAL_PERF - LOWEST_PERF))

This means:
1- the functions are not inverse for some values:
   (perf_to_khz(khz_to_perf(x)) != x)
2- cppc_cpufreq_perf_to_khz(LOWEST_PERF) can sometimes give
   a different value from LOWEST_FREQ due to integer approximation
3- it is implied that performance and frequency are proportional
   (NOMINAL_FREQ / NOMINAL_PERF) == (LOWEST_PERF / LOWEST_FREQ)

This patch changes the conversion functions to an affine function.
This fixes the 3 points above.

Suggested-by: Lukasz Luba &lt;lukasz.luba@arm.com&gt;
Suggested-by: Morten Rasmussen &lt;morten.rasmussen@arm.com&gt;
Signed-off-by: Pierre Gondois &lt;Pierre.Gondois@arm.com&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
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