<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/cpufreq/intel_pstate.c, branch v4.9</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>cpufreq: intel_pstate: Always set max P-state in performance mode</title>
<updated>2016-10-24T21:20:25+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2016-10-24T21:20:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2f1d407adab026b34a105ed27b1d4d7e910c4448'/>
<id>2f1d407adab026b34a105ed27b1d4d7e910c4448</id>
<content type='text'>
The only times at which intel_pstate checks the policy set for
a given CPU is the initialization of that CPU and updates of its
policy settings from cpufreq when intel_pstate_set_policy() is
invoked.

That is insufficient, however, because intel_pstate uses the same
P-state selection function for all CPUs regardless of the policy
setting for each of them and the P-state limits are shared between
them.  Thus if the policy is set to "performance" for a particular
CPU, it may not behave as expected if the cpufreq settings are
changed subsequently for another CPU.

That can be easily demonstrated by writing "performance" to
scaling_governor for all CPUs and then switching it to "powersave"
for one of them in which case all of the CPUs will behave as though
their scaling_governor were all "powersave" (even though the policy
still appears to be "performance" for the remaining CPUs).

Fix this problem by modifying intel_pstate_adjust_busy_pstate() to
always set the P-state to the maximum allowed by the current limits
for all CPUs whose policy is set to "performance".

Note that it still is recommended to always change the policy setting
in the same way for all CPUs even with this fix applied to avoid
confusion.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The only times at which intel_pstate checks the policy set for
a given CPU is the initialization of that CPU and updates of its
policy settings from cpufreq when intel_pstate_set_policy() is
invoked.

That is insufficient, however, because intel_pstate uses the same
P-state selection function for all CPUs regardless of the policy
setting for each of them and the P-state limits are shared between
them.  Thus if the policy is set to "performance" for a particular
CPU, it may not behave as expected if the cpufreq settings are
changed subsequently for another CPU.

That can be easily demonstrated by writing "performance" to
scaling_governor for all CPUs and then switching it to "powersave"
for one of them in which case all of the CPUs will behave as though
their scaling_governor were all "powersave" (even though the policy
still appears to be "performance" for the remaining CPUs).

Fix this problem by modifying intel_pstate_adjust_busy_pstate() to
always set the P-state to the maximum allowed by the current limits
for all CPUs whose policy is set to "performance".

Note that it still is recommended to always change the policy setting
in the same way for all CPUs even with this fix applied to avoid
confusion.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Set P-state upfront in performance mode</title>
<updated>2016-10-21T20:18:22+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2016-10-19T00:57:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a6c6ead14183ea4ec8ce7551e1f3451024b9c4db'/>
<id>a6c6ead14183ea4ec8ce7551e1f3451024b9c4db</id>
<content type='text'>
After commit a4675fbc4a7a (cpufreq: intel_pstate: Replace timers with
utilization update callbacks) the cpufreq governor callbacks may not
be invoked on NOHZ_FULL CPUs and, in particular, switching to the
"performance" policy via sysfs may not have any effect on them.  That
is a problem, because it usually is desirable to squeeze the last
bit of performance out of those CPUs, so work around it by setting
the maximum P-state (within the limits) in intel_pstate_set_policy()
upfront when the policy is CPUFREQ_POLICY_PERFORMANCE.

Fixes: a4675fbc4a7a (cpufreq: intel_pstate: Replace timers with utilization update callbacks)
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Acked-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
After commit a4675fbc4a7a (cpufreq: intel_pstate: Replace timers with
utilization update callbacks) the cpufreq governor callbacks may not
be invoked on NOHZ_FULL CPUs and, in particular, switching to the
"performance" policy via sysfs may not have any effect on them.  That
is a problem, because it usually is desirable to squeeze the last
bit of performance out of those CPUs, so work around it by setting
the maximum P-state (within the limits) in intel_pstate_set_policy()
upfront when the policy is CPUFREQ_POLICY_PERFORMANCE.

Fixes: a4675fbc4a7a (cpufreq: intel_pstate: Replace timers with utilization update callbacks)
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Acked-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Fix struct pstate_adjust_policy kerneldoc</title>
<updated>2016-10-12T18:58:14+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2016-10-11T21:07:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3954517e2f083c8aeb52bfd467b7b2c164232ffc'/>
<id>3954517e2f083c8aeb52bfd467b7b2c164232ffc</id>
<content type='text'>
It looks like the name of struct pstate_adjust_policy was updated
without updating its kerneldoc comment accordingly, so fix that
mistake.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
It looks like the name of struct pstate_adjust_policy was updated
without updating its kerneldoc comment accordingly, so fix that
mistake.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Proportional algorithm for Atom</title>
<updated>2016-10-12T18:58:13+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2016-10-06T12:07:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0843e83c1a4aa67e08f424430526c948d591d5f1'/>
<id>0843e83c1a4aa67e08f424430526c948d591d5f1</id>
<content type='text'>
The PID algorithm used by the intel_pstate driver tends to drive
performance to the minimum for workloads with utilization below the
setpoint, which is undesirable, so replace it with a modified
"proportional" algorithm on Atom.

The new algorithm will set the new P-state to be 1.25 times the
available maximum times the (frequency-invariant) utilization during
the previous sampling period except when the target P-state computed
this way is lower than the average P-state during the previous
sampling period.  In the latter case, it will increase the target by
50% of the difference between it and the average P-state to prevent
performance from dropping down too fast in some cases.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Tested-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The PID algorithm used by the intel_pstate driver tends to drive
performance to the minimum for workloads with utilization below the
setpoint, which is undesirable, so replace it with a modified
"proportional" algorithm on Atom.

The new algorithm will set the new P-state to be 1.25 times the
available maximum times the (frequency-invariant) utilization during
the previous sampling period except when the target P-state computed
this way is lower than the average P-state during the previous
sampling period.  In the latter case, it will increase the target by
50% of the difference between it and the average P-state to prevent
performance from dropping down too fast in some cases.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Tested-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Clarify comment in get_target_pstate_use_performance()</title>
<updated>2016-10-09T16:54:57+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2016-09-30T01:13:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f00593a4bdd22e0885db89df8ee8afcc6867994f'/>
<id>f00593a4bdd22e0885db89df8ee8afcc6867994f</id>
<content type='text'>
Make the comment explaining the meaning of the perf_scaled variable
in get_target_pstate_use_performance() more straightforward.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make the comment explaining the meaning of the perf_scaled variable
in get_target_pstate_use_performance() more straightforward.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Fix unsafe HWP MSR access</title>
<updated>2016-10-09T16:54:13+00:00</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2016-10-08T19:42:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f9f4872df6e1801572949f8a370c886122d4b6da'/>
<id>f9f4872df6e1801572949f8a370c886122d4b6da</id>
<content type='text'>
This is a requirement that MSR MSR_PM_ENABLE must be set to 0x01 before
reading MSR_HWP_CAPABILITIES on a given CPU. If cpufreq init() is
scheduled on a CPU which is not same as policy-&gt;cpu or migrates to a
different CPU before calling msr read for MSR_HWP_CAPABILITIES, it
is possible that MSR_PM_ENABLE was not to set to 0x01 on that CPU.
This will cause GP fault. So like other places in this path
rdmsrl_on_cpu should be used instead of rdmsrl.

Moreover the scope of MSR_HWP_CAPABILITIES is on per thread basis, so it
should be read from the same CPU, for which MSR MSR_HWP_REQUEST is
getting set.

dmesg dump or warning:

[   22.014488] WARNING: CPU: 139 PID: 1 at arch/x86/mm/extable.c:50 ex_handler_rdmsr_unsafe+0x68/0x70
[   22.014492] unchecked MSR access error: RDMSR from 0x771
[   22.014493] Modules linked in:
[   22.014507] CPU: 139 PID: 1 Comm: swapper/0 Not tainted 4.7.5+ #1
...
...
[   22.014516] Call Trace:
[   22.014542]  [&lt;ffffffff813d7dd1&gt;] dump_stack+0x63/0x82
[   22.014558]  [&lt;ffffffff8107bc8b&gt;] __warn+0xcb/0xf0
[   22.014561]  [&lt;ffffffff8107bcff&gt;] warn_slowpath_fmt+0x4f/0x60
[   22.014563]  [&lt;ffffffff810676f8&gt;] ex_handler_rdmsr_unsafe+0x68/0x70
[   22.014564]  [&lt;ffffffff810677d9&gt;] fixup_exception+0x39/0x50
[   22.014604]  [&lt;ffffffff8102e400&gt;] do_general_protection+0x80/0x150
[   22.014610]  [&lt;ffffffff817f9ec8&gt;] general_protection+0x28/0x30
[   22.014635]  [&lt;ffffffff81687940&gt;] ? get_target_pstate_use_performance+0xb0/0xb0
[   22.014642]  [&lt;ffffffff810600c7&gt;] ? native_read_msr+0x7/0x40
[   22.014657]  [&lt;ffffffff81688123&gt;] intel_pstate_hwp_set+0x23/0x130
[   22.014660]  [&lt;ffffffff81688406&gt;] intel_pstate_set_policy+0x1b6/0x340
[   22.014662]  [&lt;ffffffff816829bb&gt;] cpufreq_set_policy+0xeb/0x2c0
[   22.014664]  [&lt;ffffffff81682f39&gt;] cpufreq_init_policy+0x79/0xe0
[   22.014666]  [&lt;ffffffff81682cb0&gt;] ? cpufreq_update_policy+0x120/0x120
[   22.014669]  [&lt;ffffffff816833a6&gt;] cpufreq_online+0x406/0x820
[   22.014671]  [&lt;ffffffff8168381f&gt;] cpufreq_add_dev+0x5f/0x90
[   22.014717]  [&lt;ffffffff81530ac8&gt;] subsys_interface_register+0xb8/0x100
[   22.014719]  [&lt;ffffffff816821bc&gt;] cpufreq_register_driver+0x14c/0x210
[   22.014749]  [&lt;ffffffff81fe1d90&gt;] intel_pstate_init+0x39d/0x4d5
[   22.014751]  [&lt;ffffffff81fe13f2&gt;] ? cpufreq_gov_dbs_init+0x12/0x12

Cc: 4.3+ &lt;stable@vger.kernel.org&gt; # 4.3+
Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is a requirement that MSR MSR_PM_ENABLE must be set to 0x01 before
reading MSR_HWP_CAPABILITIES on a given CPU. If cpufreq init() is
scheduled on a CPU which is not same as policy-&gt;cpu or migrates to a
different CPU before calling msr read for MSR_HWP_CAPABILITIES, it
is possible that MSR_PM_ENABLE was not to set to 0x01 on that CPU.
This will cause GP fault. So like other places in this path
rdmsrl_on_cpu should be used instead of rdmsrl.

Moreover the scope of MSR_HWP_CAPABILITIES is on per thread basis, so it
should be read from the same CPU, for which MSR MSR_HWP_REQUEST is
getting set.

dmesg dump or warning:

[   22.014488] WARNING: CPU: 139 PID: 1 at arch/x86/mm/extable.c:50 ex_handler_rdmsr_unsafe+0x68/0x70
[   22.014492] unchecked MSR access error: RDMSR from 0x771
[   22.014493] Modules linked in:
[   22.014507] CPU: 139 PID: 1 Comm: swapper/0 Not tainted 4.7.5+ #1
...
...
[   22.014516] Call Trace:
[   22.014542]  [&lt;ffffffff813d7dd1&gt;] dump_stack+0x63/0x82
[   22.014558]  [&lt;ffffffff8107bc8b&gt;] __warn+0xcb/0xf0
[   22.014561]  [&lt;ffffffff8107bcff&gt;] warn_slowpath_fmt+0x4f/0x60
[   22.014563]  [&lt;ffffffff810676f8&gt;] ex_handler_rdmsr_unsafe+0x68/0x70
[   22.014564]  [&lt;ffffffff810677d9&gt;] fixup_exception+0x39/0x50
[   22.014604]  [&lt;ffffffff8102e400&gt;] do_general_protection+0x80/0x150
[   22.014610]  [&lt;ffffffff817f9ec8&gt;] general_protection+0x28/0x30
[   22.014635]  [&lt;ffffffff81687940&gt;] ? get_target_pstate_use_performance+0xb0/0xb0
[   22.014642]  [&lt;ffffffff810600c7&gt;] ? native_read_msr+0x7/0x40
[   22.014657]  [&lt;ffffffff81688123&gt;] intel_pstate_hwp_set+0x23/0x130
[   22.014660]  [&lt;ffffffff81688406&gt;] intel_pstate_set_policy+0x1b6/0x340
[   22.014662]  [&lt;ffffffff816829bb&gt;] cpufreq_set_policy+0xeb/0x2c0
[   22.014664]  [&lt;ffffffff81682f39&gt;] cpufreq_init_policy+0x79/0xe0
[   22.014666]  [&lt;ffffffff81682cb0&gt;] ? cpufreq_update_policy+0x120/0x120
[   22.014669]  [&lt;ffffffff816833a6&gt;] cpufreq_online+0x406/0x820
[   22.014671]  [&lt;ffffffff8168381f&gt;] cpufreq_add_dev+0x5f/0x90
[   22.014717]  [&lt;ffffffff81530ac8&gt;] subsys_interface_register+0xb8/0x100
[   22.014719]  [&lt;ffffffff816821bc&gt;] cpufreq_register_driver+0x14c/0x210
[   22.014749]  [&lt;ffffffff81fe1d90&gt;] intel_pstate_init+0x39d/0x4d5
[   22.014751]  [&lt;ffffffff81fe13f2&gt;] ? cpufreq_gov_dbs_init+0x12/0x12

Cc: 4.3+ &lt;stable@vger.kernel.org&gt; # 4.3+
Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'pm-cpufreq-sched' into pm-cpufreq</title>
<updated>2016-10-01T23:42:33+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2016-10-01T23:42:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b6e251178286eff8bbd2c01a1b6aa7a317eb3c67'/>
<id>b6e251178286eff8bbd2c01a1b6aa7a317eb3c67</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Add io_boost trace</title>
<updated>2016-09-16T21:55:30+00:00</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2016-09-14T00:41:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3ba7bcaa3657f5fe32295ebd17fbdaaf16608e2f'/>
<id>3ba7bcaa3657f5fe32295ebd17fbdaaf16608e2f</id>
<content type='text'>
Add io_boost percent to current pstate_sample tracepoint.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add io_boost percent to current pstate_sample tracepoint.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Use IOWAIT flag in Atom algorithm</title>
<updated>2016-09-14T00:28:13+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2016-09-14T00:28:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=09c448d3c61f31322c097cb4c1484778d50da399'/>
<id>09c448d3c61f31322c097cb4c1484778d50da399</id>
<content type='text'>
Modify the P-state selection algorithm for Atom processors to use
the new SCHED_CPUFREQ_IOWAIT flag instead of the questionable
get_cpu_iowait_time_us() function.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Modify the P-state selection algorithm for Atom processors to use
the new SCHED_CPUFREQ_IOWAIT flag instead of the questionable
get_cpu_iowait_time_us() function.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: constify local structures</title>
<updated>2016-09-13T00:40:24+00:00</updated>
<author>
<name>Julia Lawall</name>
<email>Julia.Lawall@lip6.fr</email>
</author>
<published>2016-09-11T13:06:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=42ce8921cca08ae8d9068968e6658cae856a99df'/>
<id>42ce8921cca08ae8d9068968e6658cae856a99df</id>
<content type='text'>
For structure types defined in the same file or local header files, find
top-level static structure declarations that have the following
properties:
1. Never reassigned.
2. Address never taken
3. Not passed to a top-level macro call
4. No pointer or array-typed field passed to a function or stored in a
variable.
Declare structures having all of these properties as const.

Done using Coccinelle.
Based on a suggestion by Joe Perches &lt;joe@perches.com&gt;.

Signed-off-by: Julia Lawall &lt;Julia.Lawall@lip6.fr&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For structure types defined in the same file or local header files, find
top-level static structure declarations that have the following
properties:
1. Never reassigned.
2. Address never taken
3. Not passed to a top-level macro call
4. No pointer or array-typed field passed to a function or stored in a
variable.
Declare structures having all of these properties as const.

Done using Coccinelle.
Based on a suggestion by Joe Perches &lt;joe@perches.com&gt;.

Signed-off-by: Julia Lawall &lt;Julia.Lawall@lip6.fr&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
