<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/cpufreq/intel_pstate.c, branch v3.19</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>intel_pstate: Add a few comments</title>
<updated>2014-12-10T23:24:42+00:00</updated>
<author>
<name>Kristen Carlson Accardi</name>
<email>kristen@linux.intel.com</email>
</author>
<published>2014-12-10T20:39:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e0d4c8f80804000eadc106bc5167b96fc6231d98'/>
<id>e0d4c8f80804000eadc106bc5167b96fc6231d98</id>
<content type='text'>
Add a few comments in the code which calculates busyness to
clarify parts of the algorithm.

Signed-off-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a few comments in the code which calculates busyness to
clarify parts of the algorithm.

Signed-off-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: add kernel parameter to force loading</title>
<updated>2014-12-10T23:23:48+00:00</updated>
<author>
<name>Ethan Zhao</name>
<email>ethan.zhao@oracle.com</email>
</author>
<published>2014-12-09T01:43:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=aa4ea34da9e7a2bc0fb98f5add3e4e52872b7d45'/>
<id>aa4ea34da9e7a2bc0fb98f5add3e4e52872b7d45</id>
<content type='text'>
To force loading on Oracle Sun X86 servers, provide one kernel command line
parameter

  intel_pstate = force

For those who are aware of the risk of no power capping capabily working
and try to get better performance with this driver.

Signed-off-by: Ethan Zhao &lt;ethan.zhao@oracle.com&gt;
Tested-by: Alexey Kodanev &lt;alexey.kodanev@oracle.com&gt;
Reviewed-by: Linda Knippers &lt;linda.knippers@hp.com&gt;
Acked-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
To force loading on Oracle Sun X86 servers, provide one kernel command line
parameter

  intel_pstate = force

For those who are aware of the risk of no power capping capabily working
and try to get better performance with this driver.

Signed-off-by: Ethan Zhao &lt;ethan.zhao@oracle.com&gt;
Tested-by: Alexey Kodanev &lt;alexey.kodanev@oracle.com&gt;
Reviewed-by: Linda Knippers &lt;linda.knippers@hp.com&gt;
Acked-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: skip this driver if Sun server has _PPC method</title>
<updated>2014-12-03T01:56:04+00:00</updated>
<author>
<name>ethan zhao</name>
<email>ethan.zhao@oracle.com</email>
</author>
<published>2014-12-01T02:32:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=966916eabfb1726fec7ea7b69f0c7f5ce366e943'/>
<id>966916eabfb1726fec7ea7b69f0c7f5ce366e943</id>
<content type='text'>
Oracle Sun X86 servers have dynamic power capping capability that works via
ACPI _PPC method etc, so skip loading this driver if Sun server has ACPI _PPC
enabled.

Signed-off-by: Ethan Zhao &lt;ethan.zhao@oracle.com&gt;
Tested-by: Linda Knippers &lt;linda.knippers@hp.com&gt;
Acked-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Oracle Sun X86 servers have dynamic power capping capability that works via
ACPI _PPC method etc, so skip loading this driver if Sun server has ACPI _PPC
enabled.

Signed-off-by: Ethan Zhao &lt;ethan.zhao@oracle.com&gt;
Tested-by: Linda Knippers &lt;linda.knippers@hp.com&gt;
Acked-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: Add CPUID for BDW-H CPU</title>
<updated>2014-11-11T23:04:38+00:00</updated>
<author>
<name>Dirk Brandewie</name>
<email>dirk.j.brandewie@intel.com</email>
</author>
<published>2014-11-06T17:50:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=43f8a966e91f387eabe85d2f2d12519c218f9dd0'/>
<id>43f8a966e91f387eabe85d2f2d12519c218f9dd0</id>
<content type='text'>
Add BDW-H to the list of supported processors.

Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add BDW-H to the list of supported processors.

Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: Add support for HWP</title>
<updated>2014-11-11T23:04:38+00:00</updated>
<author>
<name>Dirk Brandewie</name>
<email>dirk.j.brandewie@intel.com</email>
</author>
<published>2014-11-06T17:40:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2f86dc4cddcb21290ca099e1dce2a53533c86e0b'/>
<id>2f86dc4cddcb21290ca099e1dce2a53533c86e0b</id>
<content type='text'>
Add support of Hardware Managed Performance States (HWP) described in Volume 3
section 14.4 of the SDM.

With HWP enbaled intel_pstate will no longer be responsible for selecting P
states for the processor. intel_pstate will continue to register to
the cpufreq core as the scaling driver for CPUs implementing
HWP. In HWP mode intel_pstate provides three functions reporting
frequency to the cpufreq core, support for the set_policy() interface
from the core and maintaining the intel_pstate sysfs interface in
/sys/devices/system/cpu/intel_pstate.  User preferences expressed via
the set_policy() interface or the sysfs interface are forwared to the
CPU via the HWP MSR interface.

Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support of Hardware Managed Performance States (HWP) described in Volume 3
section 14.4 of the SDM.

With HWP enbaled intel_pstate will no longer be responsible for selecting P
states for the processor. intel_pstate will continue to register to
the cpufreq core as the scaling driver for CPUs implementing
HWP. In HWP mode intel_pstate provides three functions reporting
frequency to the cpufreq core, support for the set_policy() interface
from the core and maintaining the intel_pstate sysfs interface in
/sys/devices/system/cpu/intel_pstate.  User preferences expressed via
the set_policy() interface or the sysfs interface are forwared to the
CPU via the HWP MSR interface.

Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: Correct BYT VID values.</title>
<updated>2014-10-23T21:00:00+00:00</updated>
<author>
<name>Dirk Brandewie</name>
<email>dirk.j.brandewie@intel.com</email>
</author>
<published>2014-10-13T15:37:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=d022a65ed2473fac4a600e3424503dc571160a3e'/>
<id>d022a65ed2473fac4a600e3424503dc571160a3e</id>
<content type='text'>
Using a VID value that is not high enough for the requested P state can
cause machine checks. Add a ceiling function to ensure calulated VIDs
with fractional values are set to the next highest integer VID value.

The algorythm for calculating the non-trubo VID from the BIOS writers
guide is:
 vid_ratio = (vid_max - vid_min) / (max_pstate - min_pstate)
 vid = ceiling(vid_min + (req_pstate - min_pstate) * vid_ratio)

Cc: All applicable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Using a VID value that is not high enough for the requested P state can
cause machine checks. Add a ceiling function to ensure calulated VIDs
with fractional values are set to the next highest integer VID value.

The algorythm for calculating the non-trubo VID from the BIOS writers
guide is:
 vid_ratio = (vid_max - vid_min) / (max_pstate - min_pstate)
 vid = ceiling(vid_min + (req_pstate - min_pstate) * vid_ratio)

Cc: All applicable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: Fix BYT frequency reporting</title>
<updated>2014-10-23T20:59:59+00:00</updated>
<author>
<name>Dirk Brandewie</name>
<email>dirk.j.brandewie@intel.com</email>
</author>
<published>2014-10-13T15:37:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b27580b05e6f5253228debc60b8ff4a786ff573a'/>
<id>b27580b05e6f5253228debc60b8ff4a786ff573a</id>
<content type='text'>
BYT has a different conversion from P state to frequency than the core
processors.  This causes the min/max and current frequency to be
misreported on some BYT SKUs. Tested on BYT N2820, Ivybridge and
Haswell processors.

Link: https://bugzilla.yoctoproject.org/show_bug.cgi?id=6663
Cc: All applicable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
BYT has a different conversion from P state to frequency than the core
processors.  This causes the min/max and current frequency to be
misreported on some BYT SKUs. Tested on BYT N2820, Ivybridge and
Haswell processors.

Link: https://bugzilla.yoctoproject.org/show_bug.cgi?id=6663
Cc: All applicable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: Don't lose sysfs settings during cpu offline</title>
<updated>2014-10-23T20:59:59+00:00</updated>
<author>
<name>Dirk Brandewie</name>
<email>dirk.j.brandewie@intel.com</email>
</author>
<published>2014-10-13T15:37:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c034871712730a33e0267095f48b62eae958499c'/>
<id>c034871712730a33e0267095f48b62eae958499c</id>
<content type='text'>
The user may have custom settings don't destroy them during suspend.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=80651
Reported-by: Tobias Jakobi &lt;liquid.acid@gmx.net&gt;
Cc: All applicable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The user may have custom settings don't destroy them during suspend.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=80651
Reported-by: Tobias Jakobi &lt;liquid.acid@gmx.net&gt;
Cc: All applicable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Reflect current no_turbo state correctly</title>
<updated>2014-10-23T20:59:59+00:00</updated>
<author>
<name>Gabriele Mazzotta</name>
<email>gabriele.mzt@gmail.com</email>
</author>
<published>2014-10-13T15:37:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=4521e1a0ce173daa23dfef8312d09051e057ff8e'/>
<id>4521e1a0ce173daa23dfef8312d09051e057ff8e</id>
<content type='text'>
Some BIOSes modify the state of MSR_IA32_MISC_ENABLE_TURBO_DISABLE
based on the current power source for the system battery AC vs
battery. Reflect the correct current state and ability to modify the
no_turbo sysfs file based on current state of
MSR_IA32_MISC_ENABLE_TURBO_DISABLE.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=83151
Cc: All applicable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Gabriele Mazzotta &lt;gabriele.mzt@gmail.com&gt;
Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some BIOSes modify the state of MSR_IA32_MISC_ENABLE_TURBO_DISABLE
based on the current power source for the system battery AC vs
battery. Reflect the correct current state and ability to modify the
no_turbo sysfs file based on current state of
MSR_IA32_MISC_ENABLE_TURBO_DISABLE.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=83151
Cc: All applicable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Gabriele Mazzotta &lt;gabriele.mzt@gmail.com&gt;
Signed-off-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Fix setting max_perf_pct in performance policy</title>
<updated>2014-10-23T20:59:59+00:00</updated>
<author>
<name>Pali Rohár</name>
<email>pali.rohar@gmail.com</email>
</author>
<published>2014-10-15T23:16:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=36b4bed5cd8f6e17019fa7d380e0836872c7b367'/>
<id>36b4bed5cd8f6e17019fa7d380e0836872c7b367</id>
<content type='text'>
Code which changes policy to powersave changes also max_policy_pct based on
max_freq. Code which change max_perf_pct has upper limit base on value
max_policy_pct. When policy is changing from powersave back to performance
then max_policy_pct is not changed. Which means that changing max_perf_pct is
not possible to high values if max_freq was too low in powersave policy.

Test case:

$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq
800000
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3300000
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
100

$ echo powersave &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
$ echo 800000 &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
$ echo 20 &gt; /sys/devices/system/cpu/intel_pstate/max_perf_pct

$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
powersave
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
800000
$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
20

$ echo performance &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
$ echo 3300000 &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
$ echo 100 &gt; /sys/devices/system/cpu/intel_pstate/max_perf_pct

$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3300000
$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
24

And now intel_pstate driver allows to set maximal value for max_perf_pct based
on max_policy_pct which is 24 for previous powersave max_freq 800000.

This patch will set default value for max_policy_pct when setting policy to
performance so it will allow to set also max value for max_perf_pct.

Signed-off-by: Pali Rohár &lt;pali.rohar@gmail.com&gt;
Cc: All applicable &lt;stable@vger.kernel.org&gt;
Acked-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Code which changes policy to powersave changes also max_policy_pct based on
max_freq. Code which change max_perf_pct has upper limit base on value
max_policy_pct. When policy is changing from powersave back to performance
then max_policy_pct is not changed. Which means that changing max_perf_pct is
not possible to high values if max_freq was too low in powersave policy.

Test case:

$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq
800000
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3300000
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
100

$ echo powersave &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
$ echo 800000 &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
$ echo 20 &gt; /sys/devices/system/cpu/intel_pstate/max_perf_pct

$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
powersave
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
800000
$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
20

$ echo performance &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
$ echo 3300000 &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
$ echo 100 &gt; /sys/devices/system/cpu/intel_pstate/max_perf_pct

$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3300000
$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
24

And now intel_pstate driver allows to set maximal value for max_perf_pct based
on max_policy_pct which is 24 for previous powersave max_freq 800000.

This patch will set default value for max_policy_pct when setting policy to
performance so it will allow to set also max value for max_perf_pct.

Signed-off-by: Pali Rohár &lt;pali.rohar@gmail.com&gt;
Cc: All applicable &lt;stable@vger.kernel.org&gt;
Acked-by: Dirk Brandewie &lt;dirk.j.brandewie@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
