Pull SoC driver updates from Arnd Bergmann:
 "The highlights for the driver support this time are

   - Qualcomm platforms gain support for the Qualcomm Secure Execution
     Environment firmware interface to access EFI variables on certain
     devices, and new features for multiple platform and firmware
     drivers.

   - Arm FF-A firmware support gains support for v1.1 specification
     features, in particular notification and memory transaction
     descriptor changes.

   - SCMI firmware support now support v3.2 features for clock and DVFS
     configuration and a new transport for Qualcomm platforms.

   - Minor cleanups and bugfixes are added to pretty much all the active
     platforms: qualcomm, broadcom, dove, ti-k3, rockchip, sifive,
     amlogic, atmel, tegra, aspeed, vexpress, mediatek, samsung and
     more.

     In particular, this contains portions of the treewide conversion to
     use __counted_by annotations and the device_get_match_data helper"

* tag 'soc-drivers-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (156 commits)
  soc: qcom: pmic_glink_altmode: Print return value on error
  firmware: qcom: scm: remove unneeded 'extern' specifiers
  firmware: qcom: scm: add a missing forward declaration for struct device
  firmware: qcom: move Qualcomm code into its own directory
  soc: samsung: exynos-chipid: Convert to platform remove callback returning void
  soc: qcom: apr: Add __counted_by for struct apr_rx_buf and use struct_size()
  soc: qcom: pmic_glink: fix connector type to be DisplayPort
  soc: ti: k3-socinfo: Avoid overriding return value
  soc: ti: k3-socinfo: Fix typo in bitfield documentation
  soc: ti: knav_qmss_queue: Use device_get_match_data()
  firmware: ti_sci: Use device_get_match_data()
  firmware: qcom: qseecom: add missing include guards
  soc/pxa: ssp: Convert to platform remove callback returning void
  soc/mediatek: mtk-mmsys: Convert to platform remove callback returning void
  soc/mediatek: mtk-devapc: Convert to platform remove callback returning void
  soc/loongson: loongson2_guts: Convert to platform remove callback returning void
  soc/litex: litex_soc_ctrl: Convert to platform remove callback returning void
  soc/ixp4xx: ixp4xx-qmgr: Convert to platform remove callback returning void
  soc/ixp4xx: ixp4xx-npe: Convert to platform remove callback returning void
  soc/hisilicon: kunpeng_hccs: Convert to platform remove callback returning void
  ...

Pull clk driver updates from Stephen Boyd:
 "Herein lies a smallish collection of clk driver updates and some core
  clk framework changes for the merge window. The core framework changes
  are only improving the debugfs interface to allow phase adjustments
  and report which consumers of a clk there are. These are most likely
  only of interest to kernel developers.

  On the clk driver side, it's a ghastly amount of updates with only a
  handful of new clk drivers. We have a couple new clk drivers for
  Qualcomm, per usual, and a driver for Renesas, Amlogic, and TI
  respectively. The updates are spread throughout the clk drivers.

  Some highlights are fixing kunit tests for different configurations
  like lockdep and big-endian, avoiding integer overflow in rate
  settable clks, moving clk_hw_onecell_data to the end of allocations so
  that drivers don't corrupt their private data, and migrating clk
  drivers to the regmap maple tree. Otherwise it's the usual fixes to
  clk drivers that only come along with testing the drivers on real
  hardware.

  New Drivers:
   - Add clock driver for TWL6032
   - Initial support for the Qualcomm SM4450 Global Clock Controller and
     SM4450 RPMh clock controllers
   - Add Camera Clock Controller on Qualcomm SM8550
   - Add support for the Renesas RZ/G3S (R9A08G045) SoC
   - Add Amlogic s4 main clock controller support

Updates:
   - Make clk kunit tests work with lockdep
   - Fix clk gate kunit test for big-endian
   - Convert more than a handful of clk drivers to use regmap maple tree
   - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk
     implementation
   - Add consumer info to clk debugfs
   - Fix various clk drivers that have clk_hw_onecell_data not at the
     end of an allocation
   - Drop CLK_SET_RATE_PARENT for clocks with fixed-rate GPLLs across a
     variety of Qualcomm IPQ platforms
   - Add missing parent of APCS PLL on Qualcomm IPQ6018
   - Add I2C QUP6 clk on Qualcomm IPQ6018 but mark it critical to avoid
     problems with RPM
   - Implement safe source switching for a53pll and use on Qualcomm
     IPQ5332
   - Add support for Stromer Plus PLLs to Qualcomm clk driver
   - Switch Qualcomm SM8550 Video and GPU clock controllers to use OLE
     PLL configure method
   - Non critical fixes to halt bit checks in Qualcomm clk drivers
   - Add SMMU GDSC for Qualcomm MSM8998
   - Fix possible integer overflow in Qualcomm RCG frequency calculation
     code
   - Remove RPM managed clks from Qualcomm MSM8996 GCC driver
   - Add HFPLL configuration for the three HFPLLs in Qualcomm MSM8976
   - Switch Qualcomm MSM8996 CBF clock driver's remove function to
     return void
   - Fix missing dependency for s4 clock controllers
   - Select MXC_CLK when building in the CLK_IMX8QXP
   - Fixes for error handling paths in i.MX8 ACM driver
   - Move the clocks check in i.MX8 ACM driver in order to log any error
   - Drop the unused return value of clk_imx_acm_detach_pm_domains
   - Drop non-existant IMX8MP_CLK_AUDIOMIX_PDM_ROOT clock
   - Fix error handling in i.MX8MQ clock driver
   - Allow a different LCDIF1 clock parent if DT describes it for
     i.MX6SX
   - Keep the SCU resource table sorted in the i.MX8DXL rsrc driver
   - Move the elcdif PLL clock registration above lcd_clk, as it is its
     parent
   - Correct some ENET specific clocks for i.MX8DXL platform
   - Drop the VPU_UART and VPUCORE from i.MX8QM as latest HW revision
     doesn't have them
   - Remove "de-featured" MLB support from i.MX8QM/QXP/DXL platforms
   - Skip registering clocks owned by Cortex-A partition SCU-based
     platforms
   - Add CAN_1/2 to i.MX8QM and M4_0, PI_0_PWM_0 and PI_0_I2C_0 to
     i.MX8QXP resources"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits)
  clk: Fix clk gate kunit test on big-endian CPUs
  clk: si521xx: Increase stack based print buffer size in probe
  clk: mediatek: fix double free in mtk_clk_register_pllfh()
  clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data
  clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data
  clk: sifive: Allow building the driver as a module
  clk: analogbits: Allow building the library as a module
  clk: sprd: Composite driver support offset config
  clk: Allow phase adjustment from debugfs
  clk: Show active consumers of clocks in debugfs
  clk: Use device_get_match_data()
  clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider
  clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider
  clk: cdce925: Extend match support for OF tables
  clk: si570: Simplify probe
  clk: si5351: Simplify probe
  clk: rs9: Use i2c_get_match_data() instead of device_get_match_data()
  clk: clk-si544: Simplify probe() and is_valid_frequency()
  clk: si521xx: Use i2c_get_match_data() instead of device_get_match_data()
  clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS
  ...

* clk-cleanup:
  clk: si521xx: Increase stack based print buffer size in probe
  clk: Use device_get_match_data()
  clk: cdce925: Extend match support for OF tables
  clk: si570: Simplify probe
  clk: si5351: Simplify probe
  clk: rs9: Use i2c_get_match_data() instead of device_get_match_data()
  clk: clk-si544: Simplify probe() and is_valid_frequency()
  clk: si521xx: Use i2c_get_match_data() instead of device_get_match_data()
  clk: npcm7xx: Fix incorrect kfree
  clk: at91: remove unnecessary conditions
  clk: ti: fix double free in of_ti_divider_clk_setup()
  clk: keystone: pll: fix a couple NULL vs IS_ERR() checks
  clk: ralink: mtmips: quiet unused variable warning
  clk: gate: fix comment typo and grammar
  clk: asm9620: Remove 'hw' local variable that isn't checked

 - Make clk kunit tests work with lockdep
 - Fix clk gate kunit test for big-endian
 - Convert more than a handful of clk drivers to use regmap maple tree
 - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk
   implementation

* clk-renesas: (23 commits)
  clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
  clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
  clk: renesas: Add minimal boot support for RZ/G3S SoC
  clk: renesas: rzg2l: Add divider clock for RZ/G3S
  clk: renesas: rzg2l: Refactor SD mux driver
  clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
  clk: renesas: rzg2l: Add struct clk_hw_data
  clk: renesas: rzg2l: Add support for RZ/G3S PLL
  clk: renesas: rzg2l: Remove critical area
  clk: renesas: rzg2l: Fix computation formula
  clk: renesas: rzg2l: Trust value returned by hardware
  clk: renesas: rzg2l: Lock around writes to mux register
  clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
  clk: renesas: rcar-gen3: Extend SDnH divider table
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
  clk: renesas: r8a7795: Constify r8a7795_*_clks
  clk: renesas: r9a06g032: Name anonymous structs
  clk: renesas: r9a06g032: Fix kerneldoc warning
  clk: renesas: rzg2l: Use u32 for flag and mux_flags
  clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
  ...

* clk-kunit:
  clk: Fix clk gate kunit test on big-endian CPUs
  clk: Parameterize clk_leaf_mux_set_rate_parent
  clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops

* clk-regmap:
  clk: versaclock7: Convert to use maple tree register cache
  clk: versaclock5: Convert to use maple tree register cache
  clk: versaclock3: Convert to use maple tree register cache
  clk: versaclock3: Remove redundant _is_writeable()
  clk: si570: Convert to use maple tree register cache
  clk: si544: Convert to use maple tree register cache
  clk: si5351: Convert to use maple tree register cache
  clk: si5341: Convert to use maple tree register cache
  clk: si514: Convert to use maple tree register cache
  clk: cdce925: Convert to use maple tree register cache

* clk-frac-divider:
  clk: fractional-divider: tests: Add test suite for edge cases
  clk: fractional-divider: Improve approximation when zero based and export

 - Add consumer info to clk debugfs
 - Fix various clk drivers that have clk_hw_onecell_data not at the end
   of an allocation

* clk-debugfs:
  clk: Allow phase adjustment from debugfs
  clk: Show active consumers of clocks in debugfs

* clk-spreadtrum:
  clk: sprd: Composite driver support offset config

* clk-sifive:
  clk: sifive: Allow building the driver as a module
  clk: analogbits: Allow building the library as a module

* clk-counted:
  clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data
  clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data
  clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider
  clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider

* clk-qcom: (36 commits)
  clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
  clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
  clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
  clk: qcom: gcc-ipq6018: add QUP6 I2C clock
  clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
  clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
  clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
  clk: qcom: clk-alpha-pll: introduce stromer plus ops
  clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
  clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure
  clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure
  clk: qcom: Replace of_device.h with explicit includes
  clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect
  clk: qcom: cbf-msm8996: Convert to platform remove callback returning void
  clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src
  clk: qcom: Add GCC driver support for SM4450
  dt-bindings: clock: qcom: Add GCC clocks for SM4450
  ...

 - Add clock driver for TWL6032

* clk-doc:
  clk: linux/clk-provider.h: fix kernel-doc warnings and typos

* clk-amlogic:
  clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS
  clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller
  clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
  dt-bindings: clock: document Amlogic S4 SoC peripherals clock controller
  dt-bindings: clock: document Amlogic S4 SoC PLL clock controller

* clk-mediatek:
  clk: mediatek: fix double free in mtk_clk_register_pllfh()
  clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_data
  clk: mediatek: clk-mt7629: Add check for mtk_alloc_clk_data
  clk: mediatek: clk-mt7629-eth: Add check for mtk_alloc_clk_data
  clk: mediatek: clk-mt6797: Add check for mtk_alloc_clk_data
  clk: mediatek: clk-mt6779: Add check for mtk_alloc_clk_data
  clk: mediatek: clk-mt6765: Add check for mtk_alloc_clk_data

* clk-twl:
  clk: twl: add clock driver for TWL6032

* clk-imx:
  clk: imx: imx8qm/qxp: add more resources to whitelist
  clk: imx: scu: ignore clks not owned by Cortex-A partition
  clk: imx8: remove MLB support
  clk: imx: imx8qm-rsrc: drop VPU_UART/VPUCORE
  clk: imx: imx8qxp: correct the enet clocks for i.MX8DXL
  clk: imx: imx8qxp: Fix elcdif_pll clock
  clk: imx: imx8dxl-rsrc: keep sorted in the ascending order
  clk: imx: imx6sx: Allow a different LCDIF1 clock parent
  clk: imx: imx8mq: correct error handling path
  clk: imx8mp: Remove non-existent IMX8MP_CLK_AUDIOMIX_PDM_ROOT
  clk: imx: imx8: Simplify clk_imx_acm_detach_pm_domains()
  clk: imx: imx8: Add a message in case of devm_clk_hw_register_mux_parent_data_table() error
  clk: imx: imx8: Fix an error handling path in imx8_acm_clk_probe()
  clk: imx: imx8: Fix an error handling path if devm_clk_hw_register_mux_parent_data_table() fails
  clk: imx: imx8: Fix an error handling path in clk_imx_acm_attach_pm_domains()
  clk: imx: Select MXC_CLK for CLK_IMX8QXP

Pull clk fixes from Stephen Boyd:
 "Three fixes, one for the clk framework and two for clk drivers:

   - Avoid an oops in possible_parent_show() by checking for no parent
     properly when a DT index based lookup is used

   - Handle errors returned from divider_ro_round_rate() in
     clk_stm32_composite_determine_rate()

   - Fix clk_ops::determine_rate() implementation of socfpga's
     gateclk_ops that was ruining uart output because the divider
     was forgotten about"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate()
  clk: Sanitize possible_parent_show to Handle Return Value of of_clk_get_parent_name
  clk: socfpga: gate: Account for the divider in determine_rate

The clk gate kunit test checks that the implementation of the basic clk
gate reads and writes the proper bits in an MMIO register. The
implementation of the basic clk gate type uses writel() and readl()
which operate on little-endian registers. This test fails on big-endian
CPUs because the clk gate implementation writes to 'fake_reg' with
writel(), which converts the value to be written to little-endian before
storing the value in the fake register. When the test checks the bits in
the fake register on a big-endian machine it falsely assumes the format
of the register is also big-endian, when it is really always
little-endian. Suffice to say things don't work very well.

Mark 'fake_reg' as __le32 and push through endian accessor fixes
wherever the value is inspected to make this test endian agnostic.
There's a CLK_GATE_BIG_ENDIAN flag for big-endian MMIO devices, which
this test isn't using. A follow-up patch will test with and without that
flag.

Reported-by: Boqun Feng <boqun.feng@gmail.com>
Closes: https://lore.kernel.org/r/ZTLH5o0GlFBYsAHq@boqun-archlinux
Tested-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20231027225821.95833-1-sboyd@kernel.org

Increase the size of temporary print buffer on stack to fix the
following warnings reported by LKP.

Since all the input parameters of snprintf() are under control
of this driver, it is not possible to trigger and overflow here,
but since the print buffer is on stack and discarded once driver
probe() finishes, it is not an issue to increase it by 10 bytes
and fix the warning in the process. Make it so.

"
   drivers/clk/clk-si521xx.c: In function 'si521xx_probe':
>> drivers/clk/clk-si521xx.c:318:26: warning: '%d' directive output may be truncated writing between 1 and 10 bytes into a region of size 2 [-Wformat-truncation=]
      snprintf(name, 6, "DIFF%d", i);
                             ^~
   drivers/clk/clk-si521xx.c:318:21: note: directive argument in the range [0, 2147483647]
      snprintf(name, 6, "DIFF%d", i);
                        ^~~~~~~~
   drivers/clk/clk-si521xx.c:318:3: note: 'snprintf' output between 6 and 15 bytes into a destination of size 6
      snprintf(name, 6, "DIFF%d", i);
      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
"

Fixes: edc12763a3a2 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202310260412.AGASjFN4-lkp@intel.com/
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20231027085840.30098-1-marex@denx.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

The mtk_clk_register_pll_ops() currently frees the "pll" parameter.
The function has two callers, mtk_clk_register_pll() and
mtk_clk_register_pllfh().  The first one, the _pll() function relies on
the free, but for the second _pllfh() function it causes a double free
bug.

Really the frees should be done in the caller because that's where
the allocation is.

Fixes: d7964de8a8ea ("clk: mediatek: Add new clock driver to handle FHCTL hardware")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/cd7fa365-28cc-4c34-ac64-6da57c98baa6@moroto.mountain
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>