linux.git/drivers/clk, branch v5.9

clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk

2020-09-22T19:54:41+00:00

The fixed divider the emac_ptp_free_clk should be 2, not 4.

Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen 
Link: https://lore.kernel.org/r/20200831202657.8224-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd

clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSED

2020-09-22T19:26:59+00:00

The ChipID IO region has it's own clock, which is being disabled while
scanning for unused clocks. It turned out that some CPU hotplug, CPU idle
or even SOC firmware code depends on the reads from that area. Fix the
mysterious hang caused by entering deep CPU idle state by ignoring the
'chipid' clock during unused clocks scan, as there are no direct clients
for it which will keep it enabled.

Fixes: e062b571777f ("clk: exynos4: register clocks using common clock framework")
Signed-off-by: Marek Szyprowski 
Link: https://lore.kernel.org/r/20200922124046.10496-1-m.szyprowski@samsung.com
Reviewed-by: Krzysztof Kozlowski 
Acked-by: Sylwester Nawrocki 
Signed-off-by: Stephen Boyd

Merge tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes

2020-09-22T19:09:07+00:00

Pull Tegra clk driver fixes from Thierry Reding:

This is a set of small fixes for the Tegra clock driver.

* tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: Fix missing prototype for tegra210_clk_register_emc()
  clk: tegra: Always program PLL_E when enabled
  clk: tegra: Capitalization fixes

clk: tegra: Fix missing prototype for tegra210_clk_register_emc()

2020-09-21T12:09:10+00:00

Include the Tegra driver's clk.h to pull in the prototype definition for
this function so that compilers don't warn about it being missing.

Fixes: 0ac65fc946d3 ("clk: tegra: Implement Tegra210 EMC clock")
Reported-by: kernel test robot 
Signed-off-by: Thierry Reding

clk: tegra: Always program PLL_E when enabled

2020-09-21T12:09:09+00:00

Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
added checks to avoid enabling PLLs that have already been enabled by
the bootloader. However, the PLL_E configuration inherited from the
bootloader isn't necessarily the one that is needed for the kernel.

This can cause SATA to fail like this:

    [    5.310270] phy phy-sata.6: phy poweron failed --> -110
    [    5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110
    [    5.323022] tegra-ahci: probe of 70027000.sata failed with error -110

Fix this by always programming the PLL_E. This ensures that any mis-
configuration by the bootloader will be overwritten by the kernel.

Fixes: bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
Reported-by: LABBE Corentin 
Tested-by: Corentin Labbe 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

clk: tegra: Capitalization fixes

2020-09-21T12:09:08+00:00

HW, XUSB and PLL are abbreviations and should be all-uppercase.

Signed-off-by: Thierry Reding

Merge tag 'v5.9-clk-samsung-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-fixes

2020-09-15T16:17:57+00:00

Pull a Samsung clk driver fix from Sylwester Nawrocki:

 - fix for a regression in v5.9-rc1 on Odroid XU3/XU4, i.e. booting
   failure due to the DRAM controller root clock being disabled

* tag 'v5.9-clk-samsung-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Keep top BPLL mux on Exynos542x enabled

clk: samsung: Keep top BPLL mux on Exynos542x enabled

2020-09-15T11:56:51+00:00

BPLL clock must not be disabled because it is needed for proper DRAM
operation. This is normally handled by respective memory devfreq driver,
but when that driver is not yet probed or its probe has been deferred
the clock might get disabled what causes board hang. Fix this by calling
clk_prepare_enable() directly from the clock provider driver.

Cc: stable@vger.kernel.org
Signed-off-by: Marek Szyprowski 
Reviewed-by: Lukasz Luba 
Tested-by: Lukasz Luba 
Acked-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20200807133143.22748-1-m.szyprowski@samsung.com
Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422")
Signed-off-by: Sylwester Nawrocki

clk: qcom: lpass: Correct goto target in lpass_core_sc7180_probe()

2020-09-10T20:42:35+00:00

lpass_core_sc7180_probe() misses to call pm_clk_destroy() and
pm_runtime_disable() in error paths. Correct goto target to fix it.
This issue is found by code inspection.

Signed-off-by: Jing Xiangfeng 
Link: https://lore.kernel.org/r/20200827141629.101802-1-jingxiangfeng@huawei.com
Fixes: edab812d802d ("clk: qcom: lpass: Add support for LPASS clock controller for SC7180")
Signed-off-by: Stephen Boyd

clk: versatile: Add of_node_put() before return statement

2020-09-10T07:57:42+00:00

Every iteration of for_each_available_child_of_node() decrements
the reference count of the previous node, however when control is
transferred from the middle of the loop, as in the case of a return
or break or goto, there is no decrement thus ultimately resulting in
a memory leak.

Fix a potential memory leak in clk-impd1.c by inserting
of_node_put() before a return statement.

Issue found with Coccinelle.

Signed-off-by: Sumera Priyadarsini 
Link: https://lore.kernel.org/r/20200829175704.GA10998@Kaladin
Reviewed-by: Linus Walleij 
Signed-off-by: Stephen Boyd