linux.git/drivers/clk, branch v5.1-rc5

clk: imx: Fix PLL_1416X not rounding rates

2019-04-12T21:21:43+00:00

Code which initializes the "clk_init_data.ops" checks pll->rate_table
before that field is ever assigned to so it always picks
"clk_pll1416x_min_ops".

This breaks dynamic rate rounding for features such as cpufreq.

Fix by checking pll_clk->rate_table instead, here pll_clk refers to
the constant initialization data coming from per-soc clk driver.

Signed-off-by: Leonard Crestez 
Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Signed-off-by: Stephen Boyd

clk: mediatek: fix clk-gate flag setting

2019-04-12T16:41:49+00:00

CLK_SET_RATE_PARENT would be dropped.
Merge two flag setting together to correct the error.

Fixes: 5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate")
Cc: 
Signed-off-by: Weiyi Lu 
Reviewed-by: Matthias Brugger 
Signed-off-by: Stephen Boyd

clk: x86: Add system specific quirk to mark clocks as critical

2019-04-10T22:54:12+00:00

Since commit 648e921888ad ("clk: x86: Stop marking clocks as
CLK_IS_CRITICAL"), the pmc_plt_clocks of the Bay Trail SoC are
unconditionally gated off. Unfortunately this will break systems where these
clocks are used for external purposes beyond the kernel's knowledge. Fix it
by implementing a system specific quirk to mark the necessary pmc_plt_clks as
critical.

Fixes: 648e921888ad ("clk: x86: Stop marking clocks as CLK_IS_CRITICAL")
Signed-off-by: David Müller 
Signed-off-by: Hans de Goede 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Stephen Boyd

Merge tag 'meson-clk-fixes-for-5.1-v2' of https://github.com/BayLibre/clk-meson into clk-fixes

2019-03-29T22:42:34+00:00

Pull more fixes for meson clocks from Neil Armstrong:
 - clk-pll: fix rate rounding fixing meson8b boot failure
 - vid-pll-div: fix recal_rate warning and return when invalid setting

* tag 'meson-clk-fixes-for-5.1-v2' of https://github.com/BayLibre/clk-meson:
  clk: meson: vid-pll-div: remove warning and return 0 on invalid config
  clk: meson: pll: fix rounding and setting a rate that matches precisely

clk: meson: vid-pll-div: remove warning and return 0 on invalid config

2019-03-29T08:41:30+00:00

The vid_pll_div is a programmable fractional divider, but vendor gives a
limited of known configuration value and it's corresponding fraction.

Thus when at reset value (0) or unknown value, we cannot determine the
result rate.

The initial behaviour was to print a warning, but the warning triggers
at each boot and when the clock tree is refreshed.

This patch moves the print to debug and returns 0 instead of the
parent rate.

Fixes: 72dbb8c94d0d ("clk: meson: Add vid_pll divider driver")
Signed-off-by: Neil Armstrong 
Reviewed-by: Jerome Brunet 
Link: https://lkml.kernel.org/r/20190327151348.27402-1-narmstrong@baylibre.com

clk: meson: pll: fix rounding and setting a rate that matches precisely

2019-03-25T12:18:09+00:00

Make meson_clk_pll_is_better() consider a rate that precisely matches
the requested rate to be better than any previous rate (which was
smaller than the current).

Prior to commit 8eed1db1adec6a ("clk: meson: pll: update driver for the
g12a") meson_clk_get_pll_settings() returned early (before calling
meson_clk_pll_is_better()) if the rate from the current iteration
matches the requested rate precisely. After this commit
meson_clk_pll_is_better() is called unconditionally. This requires
meson_clk_pll_is_better() to work with the case where "now == rate".

This fixes a hang during boot on Meson8b / Odroid-C1 for me.

Fixes: 8eed1db1adec6a ("clk: meson: pll: update driver for the g12a")
Signed-off-by: Martin Blumenstingl 
Reviewed-by: Jerome Brunet 
Signed-off-by: Neil Armstrong 
Link: https://lkml.kernel.org/r/20190324164327.22590-2-martin.blumenstingl@googlemail.com

Merge tag 'meson-clk-fixes-for-5.1' of https://github.com/BayLibre/clk-meson into clk-fixes

2019-03-19T21:30:36+00:00

Pull a round of fixes for meson clocks from Neil Armstrong:
 - g12a: Fix VPU clock parents and mux mask
 - gxbb: Add CLK_DIVIDER_ROUND_CLOSEST to video decoder clocks

* tag 'meson-clk-fixes-for-5.1' of https://github.com/BayLibre/clk-meson:
  clk: meson-g12a: fix VPU clock parents
  clk: meson: g12a: fix VPU clock muxes mask
  clk: meson-gxbb: round the vdec dividers to closest

clk: meson-g12a: fix VPU clock parents

2019-03-19T16:38:41+00:00

First two VPU clock parents are wrong, fix it here.

Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Neil Armstrong 
Acked-by: Jerome Brunet 
Link: https://lkml.kernel.org/r/20190313135503.3198-1-narmstrong@baylibre.com

clk: meson: g12a: fix VPU clock muxes mask

2019-03-19T16:38:00+00:00

There are 8 parents, use 0x7

Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Maxime Jourdan 
Acked-by: Neil Armstrong 
Signed-off-by: Neil Armstrong 
Link: https://lkml.kernel.org/r/20190319082611.6215-1-mjourdan@baylibre.com

clk: meson-gxbb: round the vdec dividers to closest

2019-03-19T16:36:37+00:00

We want the video decoder clocks to always round to closest. While the
muxes are already using CLK_MUX_ROUND_CLOSEST, the corresponding
CLK_DIVIDER_ROUND_CLOSEST was forgotten for the dividers.

Fix this by adding the flag to the two vdec dividers.

Fixes: a565242eb9fc ("clk: meson: gxbb: add the video decoder clocks")
Signed-off-by: Maxime Jourdan 
Acked-by: Neil Armstrong 
Signed-off-by: Neil Armstrong 
Link: https://lkml.kernel.org/r/20190319102537.2043-1-mjourdan@baylibre.com