linux.git/drivers/clk, branch v4.9-rc7

Merge tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes

2016-11-16T19:10:58+00:00

Pull Allwinner clock fixes from Maxime Ripard:

Two fixes, one for the old clock code, one for the new implementation.

* tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi: Fix M factor computation for APB1
  clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent

clk: efm32gg: Pass correct type to hw provider registration

2016-11-16T19:08:55+00:00

Dan Carpenter reports that we're passing a pointer to a pointer
here when we should just be passing a pointer. Pass the right
pointer so that the of_clk_hw_onecell_get() sees the appropriate
data pointer on its end.

Reported-by: Dan Carpenter 
Cc: Stephen Boyd 
Cc: Uwe Kleine-König 
Fixes: 9337631f52a8 ("clk: efm32gg: Migrate to clk_hw based OF and registration APIs")
Signed-off-by: Stephen Boyd

clk: berlin: Pass correct type to hw provider registration

2016-11-16T19:04:17+00:00

Dan Carpenter reports that we're passing a pointer to a pointer
here when we should just be passing a pointer. Pass the right
pointer so that the of_clk_hw_onecell_get() sees the appropriate
data pointer on its end.

Reported-by: Dan Carpenter 
Cc: Jisheng Zhang 
Cc: Alexandre Belloni 
Cc: Sebastian Hesselbarth 
Cc: Stephen Boyd 
Fixes: f6475e298297 ("clk: berlin: Migrate to clk_hw based registration and OF APIs")
Signed-off-by: Stephen Boyd

clk: sunxi: Fix M factor computation for APB1

2016-11-04T07:49:46+00:00

commit cfa636886033 ("clk: sunxi: factors: Consolidate get_factors
parameters into a struct") introduced a regression for m factor
computation in sun4i_get_apb1_factors function.

The old code reassigned the "parent_rate" parameter to the targeted
divisor value and was buggy for the returned frequency but not for the
computed factors. Now, returned frequency is good but m factor is
incorrectly computed (its max value 31 is always set resulting in a
significantly slower frequency than the requested one...)

This patch simply restores the original proper computation for m while
keeping the good changes for returned rate.

Fixes: cfa636886033 ("clk: sunxi: factors: Consolidate get_factors parameters into a struct")
Signed-off-by: Stéphan Rafin 
Signed-off-by: Maxime Ripard

clk: mmp: pxa910: fix return value check in pxa910_clk_init()

2016-11-02T00:41:20+00:00

Fix the retrn value check which testing the wrong variable
in pxa910_clk_init().

Fixes: 2bc61da9f7ff ("clk: mmp: add pxa910 DT support for clock driver")
Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

clk: mmp: pxa168: fix return value check in pxa168_clk_init()

2016-11-02T00:41:20+00:00

Fix the retrn value check which testing the wrong variable
in pxa168_clk_init().

Fixes: ab08aefcd12d ("clk: mmp: add pxa168 DT support for clock driver")
Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

clk: mmp: mmp2: fix return value check in mmp2_clk_init()

2016-11-02T00:41:19+00:00

Fix the retrn value check which testing the wrong variable
in mmp2_clk_init().

Fixes: 1ec770d92a62 ("clk: mmp: add mmp2 DT support for clock driver")
Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

clk: qoriq: Don't allow CPU clocks higher than starting value

2016-11-02T00:26:15+00:00

The boot-time frequency of a CPU is considered its rated maximum, as we
have no other source of such information.  However, this was previously
only used for chips with 80% restrictions on secondary PLLs.  This
usually wasn't a problem because most chips/configs boot with a divider
of /1, with other dividers being used only for dynamic frequency
reduction.  However, at least one config (LS1021A at less than 1 GHz)
uses a different divider for top speed.  This was causing cpufreq to set
a frequency beyond the chip's rated speed.

This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs,
similar to the existing 80% limit that only applied to some.

Signed-off-by: Scott Wood 
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd

Merge tag 'v4.9-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

2016-11-02T00:08:13+00:00

Fix return value in error case of new ddrclk type.

* tag 'v4.9-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: don't return NULL when failing to register ddrclk branch

clk: imx: fix integer overflow in AV PLL round rate

2016-11-02T00:07:54+00:00

Since 'parent_rate * mfn' may overflow 32 bits, the result should be
stored using 64 bits.

The problem was discovered when trying to set the rate of the audio PLL
(pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but
the actual rate returned was 192.000570 MHz. The round rate function should
have been able to return 196.608 MHz, i.e., the desired rate.

Fixes: ba7f4f557eb6 ("clk: imx: correct AV PLL rate formula")
Cc: Anson Huang 
Signed-off-by: Emil Lundmark 
Reviewed-by: Fabio Estevam 
Acked-by: Shawn Guo 
Signed-off-by: Stephen Boyd