linux.git/drivers/clk, branch v4.9-rc3

clk: at91: Fix a return value in case of error

2016-10-20T23:37:56+00:00

If 'clk_hw_register()' fails, it is likely that we expect to return an
error instead of a valid pointer (which would mean success).

Fix commit f5644f10dcfb ("clk: at91: Migrate to clk_hw based registration
and OF APIs")

Signed-off-by: Christophe JAILLET 
Signed-off-by: Stephen Boyd

clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs

2016-10-19T20:15:05+00:00

I made a mistake as for naming for this block.  The MIO block is not
implemented for these 3 SoCs in the first place.  The current naming
will be a trouble if an SoC with both MIO and SD-ctrl blocks appear
in the future.

This driver has just been merged in the previous merge window.
Rename it before the release.

Signed-off-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd

clk: uniphier: fix memory overrun bug

2016-10-19T20:14:18+00:00

The first loop of this "for" statement writes memory beyond the
allocated clk_hw_onecell_data.

It should be:
    for (clk_num--; clk_num >= 0; clk_num--)
            ...

Or more simply:
    while (--clk_num >= 0)
            ...

Fixes: 734d82f4a678 ("clk: uniphier: add core support code for UniPhier clock driver")
Signed-off-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd

clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init

2016-10-17T22:42:58+00:00

The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
also reset controller.  It worked fine that single sysctrl/mediactrl
device node in DT can be used to initialize clock driver and populate
platform device for reset controller.  But it stops working after
commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
gets merged.  The commit sets flag OF_POPULATED during clock
initialization to skip the platform device populating for the same
device node.  On hi6220, it effectively makes hi6220-sysctrl reset
driver not probe any more.

The patch changes hi6220 sysctrl and mediactrl clock init macro from
CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using
the same hardware block can continue working.

Signed-off-by: Shawn Guo 
Tested-by: John Stultz 
Signed-off-by: Stephen Boyd

clk: mvebu: armada-37xx-periph: Fix the clock gate flag

2016-10-17T22:35:10+00:00

For the gate part of the peripheral clock setting the bit disables the
clock and clearing it enables the clock. This is not the default behavior
of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag.

Signed-off-by: Gregory CLEMENT 
Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700")
Signed-off-by: Stephen Boyd

clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.

2016-10-17T22:34:36+00:00

Fixes setting low-resolution video modes on HDMI.  Now the PLLH_PIX
divider adjusts itself until the PLLH is within bounds.

Signed-off-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: max77686: fix number of clocks setup for clk_hw based registration

2016-10-17T22:31:59+00:00

The commit 9b4cac33adc7 ("clk: max77686: Migrate to clk_hw based OF and
registration APIs") converted the driver to use the new provider API to
register clocks using clk_hw.

But unfortunately, in the conversion it missed to set the num_clks value
which lead to the following error when trying to register a clk provider:

[    1.963782] of_clk_max77686_get: invalid index 0
[    1.967460] ERROR: could not get clock /rtc@10070000:rtc_src(1)
[    1.973638] s3c-rtc 10070000.rtc: failed to find rtc source clock

Fix it by correctly set the max77686_clk_driver_data num_clks member.

Fixes: 9b4cac33adc7 ("clk: max77686: Migrate to clk_hw based OF and registration APIs")
Reported-by: Markus Reichl 
Suggested-by: Tobias Jakobi 
Signed-off-by: Javier Martinez Canillas 
Tested-by: Markus Reichl 
Reviewed-by: Chanwoo Choi 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Stephen Boyd

clk: mvebu: armada-37xx-periph: Fix the clock provider registration

2016-10-17T22:31:49+00:00

While trying using a peripheral clock on a driver, I saw that the clock
pointer returned by the provider was NULL.

The problem was a missing indirection. It was the pointer stored in the
hws array which needed to be updated not the value it contains.

Signed-off-by: Gregory CLEMENT 
Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700")
Signed-off-by: Stephen Boyd

clk: mediatek: Add hardware dependency

2016-10-17T22:22:26+00:00

Only propose the mediatek clock drivers on this platform, unless
build-testing.

Signed-off-by: Jean Delvare 
Cc: Shunli Wang 
Cc: James Liao 
Cc: Erin Lo 
Cc: Matthias Brugger 
Cc: Michael Turquette 
Reviewed-by: Matthias Brugger 
Signed-off-by: Stephen Boyd

clk: samsung: clk-exynos-audss: Fix module autoload

2016-10-17T22:21:48+00:00

If the driver is built as a module, autoload won't work because the module
alias information is not filled. So user-space can't match the registered
device with the corresponding module.

Export the module alias information using the MODULE_DEVICE_TABLE() macro.

Before this patch:

$ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias
alias:          platform:exynos-audss-clk

After this patch:

$ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias
alias:          platform:exynos-audss-clk
alias:          of:N*T*Csamsung,exynos5420-audss-clockC*
alias:          of:N*T*Csamsung,exynos5420-audss-clock
alias:          of:N*T*Csamsung,exynos5410-audss-clockC*
alias:          of:N*T*Csamsung,exynos5410-audss-clock
alias:          of:N*T*Csamsung,exynos5250-audss-clockC*
alias:          of:N*T*Csamsung,exynos5250-audss-clock
alias:          of:N*T*Csamsung,exynos4210-audss-clockC*
alias:          of:N*T*Csamsung,exynos4210-audss-clock

Fixes: 4d252fd5719b ("clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver")
Signed-off-by: Javier Martinez Canillas 
Reviewed-by: Krzysztof Kozlowski 
Tested-by: Krzysztof Kozlowski 
Signed-off-by: Stephen Boyd