linux.git/drivers/clk/x86, branch v6.7

clk: x86: Convert to platform remove callback returning void

2023-03-29T02:31:45+00:00

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König 
Link: https://lore.kernel.org/r/20230312161512.2715500-30-u.kleine-koenig@pengutronix.de
Signed-off-by: Stephen Boyd

clk: mxl: syscon_node_to_regmap() returns error pointers

2022-10-27T00:39:33+00:00

Commit 036177310bac ("clk: mxl: Switch from direct readl/writel based IO
to regmap based IO") introduced code resulting in below warning issued
by the smatch static checker.

  drivers/clk/x86/clk-lgm.c:441 lgm_cgu_probe() warn: passing zero to 'PTR_ERR'

Fix the warning by replacing incorrect IS_ERR_OR_NULL() with IS_ERR().

Fixes: 036177310bac ("clk: mxl: Switch from direct readl/writel based IO to regmap based IO")
Reported-by: Dan Carpenter 
Signed-off-by: Rahul Tanwar 
Link: https://lore.kernel.org/r/49e339d4739e4ae4c92b00c1b2918af0755d4122.1666695221.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd

clk: mxl: Fix a clk entry by adding relevant flags

2022-10-17T22:27:48+00:00

One of the clock entry "dcl" clk has some HW limitations. One is that
its rate can only by changed by changing its parent clk's rate & two is
that HW does not support enable/disable for this clk.

Handle above two limitations by adding relevant flags. Add standard flag
CLK_SET_RATE_PARENT to handle rate change and add driver internal flag
DIV_CLK_NO_MASK to handle enable/disable.

Fixes: d058fd9e8984 ("clk: intel: Add CGU clock driver for a new SoC")
Reviewed-by: Yi xin Zhu 
Signed-off-by: Rahul Tanwar 
Link: https://lore.kernel.org/r/a4770e7225f8a0c03c8ab2ba80434a4e8e9afb17.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd

clk: mxl: Add option to override gate clks

2022-10-17T22:27:36+00:00

In MxL's LGM SoC, gate clocks can be controlled either from CGU clk driver
i.e. this driver or directly from power management driver/daemon. It is
dependent on the power policy/profile requirements of the end product.

To support such use cases, provide option to override gate clks enable/disable
by adding a flag GATE_CLK_HW which controls if these gate clks are controlled
by HW i.e. this driver or overridden in order to allow it to be controlled
by power profiles instead.

Reviewed-by: Yi xin Zhu 
Signed-off-by: Rahul Tanwar 
Link: https://lore.kernel.org/r/bdc9c89317b5d338a6c4f1d49386b696e947a672.1665642720.git.rtanwar@maxlinear.com
[sboyd@kernel.org: Add braces on many line if-else]
Signed-off-by: Stephen Boyd

clk: mxl: Remove redundant spinlocks

2022-10-17T21:17:37+00:00

Patch 1/4 of this patch series switches from direct readl/writel
based register access to regmap based register access. Instead
of using direct readl/writel, regmap API's are used to read, write
& read-modify-write clk registers. Regmap API's already use their
own spinlocks to serialize the register accesses across multiple
cores in which case additional driver spinlocks becomes redundant.

Hence, remove redundant spinlocks from driver in this patch 2/4.

Reviewed-by: Yi xin Zhu 
Signed-off-by: Rahul Tanwar 
Link: https://lore.kernel.org/r/a8a02c8773b88924503a9fdaacd37dd2e6488bf3.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd

clk: mxl: Switch from direct readl/writel based IO to regmap based IO

2022-10-17T21:17:37+00:00

Earlier version of driver used direct io remapped register read
writes using readl/writel. But we need secure boot access which
is only possible when registers are read & written using regmap.
This is because the security bus/hook is written & coupled only
with regmap layer.

Switch the driver from direct readl/writel based register accesses
to regmap based register accesses.

Additionally, update the license headers to latest status.

Reviewed-by: Yi xin Zhu 
Signed-off-by: Rahul Tanwar 
Link: https://lore.kernel.org/r/2610331918206e0e3bd18babb39393a558fb34f9.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd

platform/x86: Drop the PMC_ATOM Kconfig option

2022-06-12T12:41:22+00:00

The def_bool y PMC_ATOM Kconfig option provides a couple of symbols used
by the code enabled by the X86_INTEL_LPSS option and it registers some
clocks. These clocks are only registered on Bay Trail, Cherry Trail and
Brasswell Intel SoCs and kernels targeting these SoCs must always have
the X86_INTEL_LPSS option enabled otherwise many things will not work.

Building the PMC_ATOM code on kernels which are not targeting the
mentioned SoCs and which do not have the X86_INTEL_LPSS enabled is
not useful.

This means that we can simplify things by replacing the PMC_ATOM Kconfig
option in Makefiles with X86_INTEL_LPSS and then drop the option.

Cc: Paul Gortmaker 
Signed-off-by: Hans de Goede 
Acked-by: Andy Shevchenko 
Acked-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20220503140207.101218-2-hdegoede@redhat.com

clk: x86: Fix clk_gate_flags for RV_CLK_GATE

2022-01-07T01:57:53+00:00

In newer SoC we have to clear bit for disabling 48MHz oscillator
clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable
and disable of 48MHz clock.

Signed-off-by: Ajit Kumar Pandey 
Reviewed-by: Mario Limonciello 
Link: https://lore.kernel.org/r/20211212180527.1641362-6-AjitKumar.Pandey@amd.com
Signed-off-by: Stephen Boyd

clk: x86: Use dynamic con_id string during clk registration

2022-01-07T01:57:52+00:00

Replace hard coded con_id string with fch_data->name. We have clk
consumers looking up with different clock names, hence use dynamic
con_id string during clk lookup registration. fch_data->name will
be initialized in acpi driver based on fmw property value.

Signed-off-by: Ajit Kumar Pandey 
Reviewed-by: Mario Limonciello 
Link: https://lore.kernel.org/r/20211212180527.1641362-5-AjitKumar.Pandey@amd.com
Signed-off-by: Stephen Boyd

x86: clk: clk-fch: Add support for newer family of AMD's SOC

2022-01-07T01:57:52+00:00

FCH controller clock configuration slightly differs across AMD's
SOC architectures. Newer family of SOC only support a 48MHz fix
clock while stoney SOC family has a clk_mux to choose 48MHz and
25 MHz clk. At present fixed clk support is only enabled for RV
architecture using "is-rv" device property initialized from boot
loader. This limit 48MHz fixed clock gate support to RV platform
unless we add similar device property in boot loader for other
architectures.

Add pci_device_id table with Stoney platform id and replace "is-rv"
device property check with pci id match to add clk mux support with
25MHz and 48MHz clk support based on clk mux selection. This enable
48Mhz fixed fch clock support by default on all newer SOC's except
stoney. Also replace RV with FIXED as a generic naming conventions
across all platforms and changed module description.

Signed-off-by: Ajit Kumar Pandey 
Reviewed-by: Mario Limonciello 
Link: https://lore.kernel.org/r/20211212180527.1641362-2-AjitKumar.Pandey@amd.com
Signed-off-by: Stephen Boyd