linux.git/drivers/clk/ti, branch v3.17

clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate

2014-08-21T15:04:16+00:00

Check for valid parameters in check rate. Else, we end up getting
errors.

This occurs as part of the inital clock tree update of child clock
nodes where new_rate could be 0 for non functional clocks.

Fixes: 9ac33b0ce81fa48 (" CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Nishanth Menon 
Signed-off-by: Tero Kristo

clk: ti: divider: Provide error check for incoming parameters in set_rate

2014-08-21T15:04:16+00:00

Check for valid parameters in check rate. Else, we end up getting errors
like:
[    0.000000] Division by zero in kernel.
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1
[    0.000000] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[    0.000000] [] (show_stack) from [] (dump_stack+0x78/0x94)
[    0.000000] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
[    0.000000] [] (Ldiv0) from [] (ti_clk_divider_set_rate+0x14/0x14c)
[    0.000000] [] (ti_clk_divider_set_rate) from [] (clk_change_rate+0x138/0x180)
[    0.000000] [] (clk_change_rate) from [] (clk_change_rate+0x108/0x180)

This occurs as part of the inital clock tree update of child clock nodes
where new_rate could be 0 for non functional clocks.

Fixes: b4761198bfaf296 ("CLK: ti: add support for ti divider-clock")
Signed-off-by: Nishanth Menon 
Signed-off-by: Tero Kristo

Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux

2014-08-04T18:44:20+00:00

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.17 are mostly additions of new clock
  drivers and fixes/enhancements to existing clock drivers.  There are
  also some non-critical fixes and improvements to the framework core.

  Changes to the clock framework core include:
   - improvements to printks on errors
   - flattening the previously hierarchal structure of per-clock entries
     in debugfs
   - allow per-clock debugfs entries that are specific to a particular
     clock driver
   - configure initial clock parent and/or initial clock rate from
     Device Tree
   - several feature enhancements to the composite clock type
   - misc fixes

  New clock drivers added include:
   - TI Palmas PMIC
   - Allwinner A23 SoC
   - Qualcomm APQ8084 and IPQ8064 SoCs
   - Rockchip rk3188, rk3066 and rk3288 SoCs
   - STMicroelectronics STiH407 SoC
   - Cirrus Logic CLPS711X SoC

  Many fixes, feature enhancements and further clock tree support for
  existing clock drivers also were merged, such as Samsung's "ARMCLK
  down" power saving feature for their Exynos4 & Exynos5 SoCs"

* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: Add missing of_clk_set_defaults export
  clk: checking wrong variable in __set_clk_parents()
  clk: Propagate any error return from debug_init()
  clk: clps711x: Add DT bindings documentation
  clk: Add CLPS711X clk driver
  clk: st: Use round to closest divider flag
  clk: st: Update frequency tables for fs660c32 and fs432c65
  clk: st: STiH407: Support for clockgenA9
  clk: st: STiH407: Support for clockgenD0/D2/D3
  clk: st: STiH407: Support for clockgenC0
  clk: st: Add quadfs reset handling
  clk: st: Add polarity bit indication
  clk: st: STiH407: Support for clockgenA0
  clk: st: STiH407: Support for A9 MUX Clocks
  clk: st: STiH407: Support for Flexgen Clocks
  clk: st: Adds Flexgen clock binding
  clk: st: Remove uncessary (void *) cast
  clk: st: use static const for clkgen_pll_data tables
  clk: st: use static const for stm_fs tables
  clk: st: Update ST clock binding documentation
  ...

clk: ti: clk-7xx: Correct ABE DPLL configuration

2014-07-31T15:36:58+00:00

ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.

Signed-off-by: Peter Ujfalusi 
Acked-by: Tero Kristo 
Signed-off-by: Mike Turquette

Merge branch 'for-v3.17/ti-clk-driver' of github.com:t-kristo/linux-pm into clk-next-ti

2014-07-25T22:37:40+00:00

CLK: ti: dra7: Initialize USB_DPLL

2014-07-02T14:08:26+00:00

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Also program USB_DLL_M2 output to half rate.

CC: Mike Turquette 
CC: Tero Kristo 
Signed-off-by: Roger Quadros 
Signed-off-by: Tero Kristo

clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock

2014-06-19T11:52:32+00:00

When setting the rate of a clock, by default the clock framework will
change the parent of the clock to the most suitable one in
__clk_mux_determine_rate() (most suitable by looking at the clock rate).

This is a rather dangerous default, and causes problems on AM43x when
using display and ethernet. There are multiple ways to select the clock
muxes on AM43x, and some of those clock paths have the same source
clocks for display and ethernet. When changing the clock rate for the
display subsystem, the clock framework decides to change the display mux
from the dedicated display PLL to a shared PLL which is used by the
ethernet, and then changes the rate of the shared PLL, breaking the
ethernet.

As I don't think there ever is a case where we want the clock framework
to automatically change the parent clock of a clock mux, this patch sets
the CLK_SET_RATE_NO_REPARENT for all ti,mux-clocks.

Signed-off-by: Tomi Valkeinen 
Reviewed-by: Paul Walmsley 
Tested-by: Felipe Balbi 
Signed-off-by: Tero Kristo

clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled

2014-06-19T11:52:31+00:00

Define ti_clk_register_dpll_x2() and of_ti_am3_dpll_x2_setup() if
AM43XX is defined.

Fixes the below boot issue.

[    2.157258] gpmc_l3_clk not enabled
[    2.161194] gpmc_l3_clk not enabled
[    2.164896] Division by zero in kernel.
[    2.169055] CPU: 0 PID: 321 Comm: kworker/u2:2 Tainted: G        W     3.16.0-rc1-00008-g4c0e520 #273
[    2.178880] Workqueue: deferwq deferred_probe_work_func
[    2.184459] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[    2.192752] [] (show_stack) from [] (dump_stack+0x80/0x9c)
[    2.200486] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
[    2.207678] [] (Ldiv0) from [] (gpmc_calc_divider+0x24/0x40)
[    2.215490] [] (gpmc_calc_divider) from [] (gpmc_cs_set_timings+0x18/0x474)
[    2.224783] [] (gpmc_cs_set_timings) from [] (gpmc_nand_init+0x74/0x1a8)
[    2.233791] [] (gpmc_nand_init) from [] (gpmc_probe+0x52c/0x874)
[    2.242089] [] (gpmc_probe) from [] (platform_drv_probe+0x18/0x48)
[    2.250534] [] (platform_drv_probe) from [] (driver_probe_device+0x104/0x22c)
[    2.259988] [] (driver_probe_device) from [] (bus_for_each_drv+0x44/0x8c)
[    2.269087] [] (bus_for_each_drv) from [] (device_attach+0x74/0x8c)
[    2.277620] [] (device_attach) from [] (bus_probe_device+0x88/0xb0)
[    2.286074] [] (bus_probe_device) from [] (deferred_probe_work_func+0x60/0x90)
[    2.295611] [] (deferred_probe_work_func) from [] (process_one_work+0x1b4/0x4bc)
[    2.305288] [] (process_one_work) from [] (worker_thread+0x148/0x550)
[    2.313954] [] (worker_thread) from [] (kthread+0xc8/0xe4)
[    2.321628] [] (kthread) from [] (ret_from_fork+0x14/0x2c)

Signed-off-by: Roger Quadros 
Reported-by: Tony Lindgren 
Signed-off-by: Tero Kristo

clk: ti: dra7: return error code in failure case

2014-06-19T11:52:31+00:00

Add a returned error code in the MAX_APLL_WAIT_TRIES case.  Remove the
updating of the return variable r to 0 if MAX_APLL_WAIT_TRIES is not yet
reached, because r is already 0 at this point.

Signed-off-by: Julia Lawall 
Signed-off-by: Tero Kristo

clk: ti: apll: not allocating enough data

2014-06-19T11:52:31+00:00

There is a cut and paste bug here which will lead to memory corruption
because we don't allocate enough data.

Fixes: 4d008589e271 ('CLK: TI: APLL: add support for omap2 aplls')
Signed-off-by: Dan Carpenter 
Signed-off-by: Tero Kristo