linux.git/drivers/clk/tegra, branch v5.5

clk: tegra: Fix double-free in tegra_clk_init()

2019-12-24T08:01:06+00:00

It's unlikely to happen in practice ever, but makes static checkers happy.

Fixes: 535f296d47de ("clk: tegra: Add suspend and resume support on Tegra210")
Reported-by: Stephen Boyd 
Signed-off-by: Dmitry Osipenko 
Link: https://lkml.kernel.org/r/20191210020512.6088-1-digetx@gmail.com
Acked-by: Thierry Reding 
Signed-off-by: Stephen Boyd

clk: tegra: Use match_string() helper to simplify the code

2019-11-13T23:03:27+00:00

match_string() returns the array index of a matching string.
Use it instead of the open-coded implementation.

Signed-off-by: YueHaibing 
Link: https://lkml.kernel.org/r/20191109034226.21044-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd

clk: tegra: Fix build error without CONFIG_PM_SLEEP

2019-11-11T13:53:05+00:00

If CONFIG_PM_SLEEP is n, build fails:

drivers/clk/tegra/clk-tegra210.c:3426:13: error:
 tegra210_clk_suspend undeclared here (not in a function); did you mean tegra_clk_ndspeed?
  .suspend = tegra210_clk_suspend,
             ^~~~~~~~~~~~~~~~~~~~
             tegra_clk_ndspeed
drivers/clk/tegra/clk-tegra210.c:3427:12: error:
 tegra210_clk_resume undeclared here (not in a function); did you mean tegra210_clk_suspend?
  .resume = tegra210_clk_resume,

Use ifdef to guard this.

Reported-by: Hulk Robot 
Fixes: 27d10d548c04 ("clk: tegra: Add suspend and resume support on Tegra210")
Signed-off-by: YueHaibing 
Signed-off-by: Thierry Reding

clk: tegra: Optimize PLLX restore on Tegra20/30

2019-11-11T13:53:04+00:00

There is no need to re-configure PLLX if its configuration in unchanged
on return from suspend / cpuidle, this saves 300us if PLLX is already
enabled (common case for cpuidle).

Signed-off-by: Dmitry Osipenko 
Acked-by: Peter De Schrijver 
Signed-off-by: Thierry Reding

clk: tegra: Add suspend and resume support on Tegra210

2019-11-11T13:53:04+00:00

All the CAR controller settings are lost on suspend when core power goes
off. This implement saving and restoring context for all PLLs and clocks
during system suspend and resume to have the clocks back to same state
for normal operation.

Clock driver suspend and resume are registered as syscore_ops as clocks
restore need to happen before the other drivers resume to have all their
clocks back to the same state as before suspend.

Signed-off-by: Sowjanya Komatineni 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

clk: tegra: Share clk and rst register defines with Tegra clock driver

2019-11-11T13:53:04+00:00

Move CLK_OUT_ENB and RST_DEVICES registers to clk.h to share these with
Tegra clock driver.

Signed-off-by: Sowjanya Komatineni 
Signed-off-by: Thierry Reding

clk: tegra: Use fence_udelay() during PLLU init

2019-11-11T13:53:03+00:00

This patch uses fence_udelay rather than udelay during PLLU
initialization to ensure writes to clock registers happens before
waiting for specified delay.

Acked-by: Thierry Reding 
Signed-off-by: Sowjanya Komatineni 
Signed-off-by: Thierry Reding

clk: tegra: clk-dfll: Add suspend and resume support

2019-11-11T13:53:03+00:00

This patch implements DFLL suspend and resume operation.

During system suspend entry, CPU clock will switch CPU to safe
clock source of PLLP and disables DFLL clock output.

DFLL driver suspend confirms DFLL disable state and errors out on
being active.

DFLL is re-initialized during the DFLL driver resume as it goes
through complete reset during suspend entry.

Acked-by: Thierry Reding 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Sowjanya Komatineni 
Signed-off-by: Thierry Reding

clk: tegra: clk-super: Add restore-context support

2019-11-11T13:53:03+00:00

This patch implements restore_context for clk_super_mux and clk_super.

During system supend, core power goes off the and context of Tegra
CAR registers is lost.

So on system resume, context of super clock registers are restored
to have them in same state as before suspend.

Acked-by: Thierry Reding 
Signed-off-by: Sowjanya Komatineni 
Signed-off-by: Thierry Reding

clk: tegra: clk-super: Fix to enable PLLP branches to CPU

2019-11-11T13:53:03+00:00

This patch has a fix to enable PLLP branches to CPU before changing
the CPU cluster clock source to PLLP for Gen5 Super clock and
disables PLLP branches to CPU when not in use.

During system suspend entry and exit, CPU source will be switched
to PLLP and this needs PLLP branches to be enabled to CPU prior to
the switch.

On system resume, warmboot code enables PLLP branches to CPU and
powers up the CPU with PLLP clock source.

Acked-by: Thierry Reding 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Sowjanya Komatineni 
Signed-off-by: Thierry Reding