linux.git/drivers/clk/tegra, branch v3.15 Linux kernel source tree Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes 2014-05-28T04:11:08+00:00 Mike Turquette mturquette@linaro.org 2014-05-28T04:11:08+00:00 5178438041cc94680e606e5a9c6d1ad9c911199b PLLE fixes for 3.15 
PLLE fixes for 3.15
clk: tegra: Fix wrong value written to PLLE_AUX 2014-05-16T22:49:23+00:00 Tuomas Tynkkynen ttynkkynen@nvidia.com 2014-05-16T13:50:20+00:00 d2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 The value written to PLLE_AUX was incorrect due to a wrong variable being used. Without this fix SATA does not work. Cc: stable@vger.kernel.org Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved changelog] 
The value written to PLLE_AUX was incorrect due to a wrong variable
being used. Without this fix SATA does not work.

Cc: stable@vger.kernel.org
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: improved changelog]
clk: tegra: remove non-existent clocks 2014-04-24T13:36:50+00:00 Stephen Warren swarren@nvidia.com 2014-04-01T20:13:16+00:00 9ba71705706aa83bcd7f9b74ae2d167da934c951 The Tegra124 clock driver currently provides 3 clocks that don't actually exist; 2 for NAND and one for UART5/UARTE. Delete these. Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
The Tegra124 clock driver currently provides 3 clocks that don't actually
exist; 2 for NAND and one for UART5/UARTE. Delete these.

Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
clk: tegra: Fix enabling of PLLE 2014-04-17T11:12:46+00:00 Thierry Reding treding@nvidia.com 2014-04-04T13:55:15+00:00 4ccc402ece35695dd2884ec0b652d52ae0230f13 When enabling the PLLE as its final step, clk_plle_enable() would accidentally OR in the value previously written to the PLLE_SS_CTRL register. Signed-off-by: Thierry Reding <treding@nvidia.com> 
When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Introduce divider mask and shift helpers 2014-04-17T11:12:40+00:00 Thierry Reding treding@nvidia.com 2014-04-04T13:55:14+00:00 c61e4e75b95bda4c6fec134aa9f08b5629b532e6 Add div{m,n,p}_shift() and div{m,n,p}_mask_shifted() helpers to make the code that modifies the m-, n- and p-divider fields of PLLs shorter and easier to read. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Add div{m,n,p}_shift() and div{m,n,p}_mask_shifted() helpers to make the
code that modifies the m-, n- and p-divider fields of PLLs shorter and
easier to read.

Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Fix PLLE programming 2014-04-17T11:12:34+00:00 Thierry Reding treding@nvidia.com 2014-04-04T13:55:13+00:00 d0f02ce3b1685ef6ffe43692034599790f83e7ab PLLE has M, N and P divider shift and width parameters that differ from the defaults. Furthermore, when clearing the M, N and P divider fields the corresponding masks were never shifted, thereby clearing only the lowest bits of the register. This lead to a situation where the PLLE programming would only work if the register hadn't been touched before. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> 
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where the PLLE
programming would only work if the register hadn't been touched before.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Merge branch 'clk-fixes' into clk-next 2014-02-25T07:07:53+00:00 Mike Turquette mturquette@linaro.org 2014-02-25T07:07:53+00:00 ad077ceb8a90c7ef1fc15758ed3811448181ee80 






clk: tegra: Staticize tegra_clk_periph_no_gate_ops
2014-02-23T22:46:05+00:00

Sachin Kamat
sachin.kamat@linaro.org

2014-01-15T05:43:25+00:00

22e5de816b49f1c75c1f1480a99d1c06d46fbe21

tegra_clk_periph_no_gate_ops is a local symbol.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>





tegra_clk_periph_no_gate_ops is a local symbol.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>







clk: tegra124: remove gr2d and gr3d clocks
2014-02-20T17:10:58+00:00

Peter De Schrijver
pdeschrijver@nvidia.com

2014-02-20T08:49:34+00:00

c7fbd4158433c1c910c62850247728cb05a94e42

Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the
vic03 and gpu clocks respectively.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>





Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the
vic03 and gpu clocks respectively.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>







clk: tegra: Fix vic03 mux index
2014-02-20T08:45:28+00:00

Peter De Schrijver
pdeschrijver@nvidia.com

2014-02-19T18:48:56+00:00

a9952a76bc0c24b3c9d355c053e001b8a3b65dd3

The vic03 mux uses a linear mapping.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>





The vic03 mux uses a linear mapping.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>