linux.git/drivers/clk/tegra, branch v3.14 Linux kernel source tree clk: tegra124: remove gr2d and gr3d clocks 2014-02-20T17:10:58+00:00 Peter De Schrijver pdeschrijver@nvidia.com 2014-02-20T08:49:34+00:00 c7fbd4158433c1c910c62850247728cb05a94e42 Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the vic03 and gpu clocks respectively. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> 
Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the
vic03 and gpu clocks respectively.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: Fix vic03 mux index 2014-02-20T08:45:28+00:00 Peter De Schrijver pdeschrijver@nvidia.com 2014-02-19T18:48:56+00:00 a9952a76bc0c24b3c9d355c053e001b8a3b65dd3 The vic03 mux uses a linear mapping. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> 
The vic03 mux uses a linear mapping.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: use max divider if divider overflows 2014-02-17T14:18:34+00:00 Andrew Bresticker abrestic@chromium.org 2013-12-27T00:44:27+00:00 3de5bdfb4cb3bd99052a4ffaee358189779be042 When requesting a rate less than the minimum clock rate for a divider, use the maximum divider value instead of bailing out with an error. This matches the behavior of the generic clock divider. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> 
When requesting a rate less than the minimum clock rate for a divider,
use the maximum divider value instead of bailing out with an error.
This matches the behavior of the generic clock divider.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
clk: tegra: cclk_lp has a pllx/2 divider 2014-02-17T14:18:28+00:00 Andrew Bresticker abrestic@chromium.org 2013-12-27T00:44:26+00:00 88b4bd7071ac06e321b4bf4bdb8c69db40182c5a When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> 
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2.  Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
clk: tegra: fix sdmmc clks on Tegra1x4 2014-02-17T14:18:23+00:00 Andrew Bresticker abrestic@chromium.org 2013-12-27T00:44:25+00:00 20e7c323abac390deb35248705807bd844590048 The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> 
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with
6 parents.  Add support for tegra_clk_sdmmc*_8 and switch Tegra114
and Tegra124 to use these clocks instead.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
clk: tegra: fix host1x clock on Tegra124 2014-02-17T14:18:16+00:00 Mark Zhang markz@nvidia.com 2013-12-27T00:44:24+00:00 82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874 The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents. Change thte id to tegra_clk_host1x_8 so that the correct clock gets registered. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> 
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
clk: tegra: PLLD2 fixes for hdmi 2014-02-17T14:18:11+00:00 David Ung davidu@nvidia.com 2013-12-27T00:44:23+00:00 0e766c2d9fc8cd2ad0e0fe97ff4e264cb686fc32 Set correct pll_d2_out0 divider and correct the p div values for pll_d2. Signed-off-by: David Ung <davidu@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> 
Set correct pll_d2_out0 divider and correct the p div values for pll_d2.

Signed-off-by: David Ung <davidu@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
clk: tegra: Fix PLLD mnp table 2014-02-17T14:18:06+00:00 Rhyland Klein rklein@nvidia.com 2013-12-27T00:44:22+00:00 67fc26bfd7a265883fd0804f24f6287d16769e3d PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> 
PLLD was using the same mnp table as PLLP.  Fix it to use its own
table which is different from PLLP's.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
clk: tegra: Fix PLLP rate table 2014-02-17T14:18:02+00:00 Gabe Black gabeblack@chromium.org 2013-12-27T00:44:21+00:00 2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a This table had settings for 216MHz, but PLLP is (and is supposed to be) configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is not set, the kernel will panic in clk_pll_recalc_rate(). Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> 
This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz.  If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
clk: tegra: Correct clock number for UARTE 2014-02-17T14:14:32+00:00 Thierry Reding thierry.reding@gmail.com 2013-12-02T11:30:25+00:00 2edf3e035302776e4756e446baf3b6c7b94c3698 UARTE has clock number 66. Number 65 is the right one for UARTD. Signed-off-by: Thierry Reding <treding@nvidia.com> 
UARTE has clock number 66. Number 65 is the right one for UARTD.

Signed-off-by: Thierry Reding <treding@nvidia.com>