linux.git/drivers/clk/tegra, branch master

Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

2026-08-17T16:28:08+00:00

Pull clk patches from Brian Masney:

 - New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS),
   UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree
   bindings. Si549 support was added to the existing si544 driver.
 - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha
   EN7523 PCIe PERSTOUT reset lines.
 - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to
   the existing optional variant, and exports
   devm_clk_hw_register_composite_pdata() for modular drivers.
 - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1
   support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL
   charge pump/lock parameter programming during dynamic reconfiguration.
 - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in
   the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted
   gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on
   registration failure, a prepare reference leak in the palmas driver,
   unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in
   pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a
   clocking-wizard clock difference detection bug.
 - Various cleanups across tegra, st, and mvebu providers to stop misusing the
   consumer clock API, along with other minor fixes and improvements.

Signed-off-by: Brian Masney 

* tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits)
  clk: tegra: set up proper EMC clock implementation for Tegra114
  clk: clocking-wizard: remove 20kHz restriction
  clk: clocking-wizard: optimize clock search
  clk: clocking-wizard: fix clock difference detection
  clk: mediatek: mt8135: Fix inverted gate control for devapc_ck
  clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig
  clk: tegra: support 48MHz clock for pll_p_out1
  clk: aspeed: add AST2700 PECI clock
  dt-bindings: clock: ast2700: add PECI clock
  clk: mediatek: Add mt8173-mfgtop driver
  dt-bindings: clock: mediatek: Add mt8173 mfgtop
  clk: tegra: clean-up simple provider misuse of the consumer API
  clk: st: clean-up simple provider misuse of the consumer API
  clk: mvebu: clean-up simple provider misuse of the consumer API
  clk: remove conditional return with no effect
  clk: Add devm_clk_bulk_get_enable()
  clk: en7523: add support for dedicated PCIe PERSTOUT reset
  dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT
  arm64: dts: cix: sky1: add audss cru
  reset: cix: add sky1 audss auxiliary reset driver
  ...

Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

2026-08-17T16:27:10+00:00

Pull clk patches picked up by Brian Masney:

Here's various improvements and fixes for the clk subsystem that was posted prior
to the opening of the last merge window.

- Add spread spectrum clock (SSC) support to the clk framework, including a new
  assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum()
  API with KUnit tests (Peng Fan)
- Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a
  common SCMI clock header (Peng Fan)
- Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and
  reset generator (Xuyang Dong)
- Add clk_determine_rate_noop() helper for clock drivers that can do any rate,
  and convert existing open-coded implementations across hisilicon, imx, qcom,
  renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain
  drivers (Brian Masney)
- Add kernel-doc documentation for struct clk_core and the core clock flags,
  and wire up clk identifiers into the documentation build (Brian Masney)
- Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum
  rate for large rate requests, with KUnit tests (Lad Prabhakar)
- Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64
  return values, incorrect PLL_CTL1_FRAC bit field width, and broken
  determine_rate logic (Joey Lu)
- Support unique clock names for multi-socket Tegra platforms (Jon Hunter)
- Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev)
- Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov,
  Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak,
  Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König,
  William Theesfeld, Xuyang Dong, and Yu-Chun Lin

Signed-off-by: Brian Masney 
[sboyd@kernel.org: Fix allmodconfig modpost failure in scmi]

* tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux: (53 commits)
  pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop()
  pmdomain: mediatek: airoha: use clk_determine_rate_noop()
  phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop()
  clk: sprd: use clk_determine_rate_noop()
  clk: scpi: use clk_determine_rate_noop()
  clk: samsung: acpm: use clk_determine_rate_noop()
  clk: rp1: use clk_determine_rate_noop()
  clk: renesas: rzg2l-cpg: use clk_determine_rate_noop()
  clk: qcom: smd-rpm: use clk_determine_rate_noop()
  clk: qcom: rpmh: use clk_determine_rate_noop()
  clk: qcom: rpm: use clk_determine_rate_noop()
  clk: imx: scu: use clk_determine_rate_noop()
  clk: hisilicon: hi3660-stub: use clk_determine_rate_noop()
  clk: add clk_determine_rate_noop()
  clk: imx: scu: drop redundant init.ops variable assignment
  clk: test: convert constants to use HZ_PER_MHZ
  docs: clk: include some identifiers to keep documentation up to date
  clk: add kernel docs for struct clk_core
  clk: add kernel docs for the core flags
  clk: hisilicon: allow COMPILE_TEST builds
  ...

clk: tegra: set up proper EMC clock implementation for Tegra114

2026-07-28T15:31:34+00:00

Remove current emc and emc_mux clocks and replace them with the proper EMC
clock implementation for correct EMC driver support.

Acked-by: Thierry Reding 
Signed-off-by: Svyatoslav Ryhel 
Reviewed-by: Mikko Perttunen 
Signed-off-by: Brian Masney

clk: tegra: support 48MHz clock for pll_p_out1

2026-07-28T15:25:30+00:00

UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported by kernel
and causes BUG() early on. Add 48MHz clock support for pll_p_out1.

Acked-by: Thierry Reding 
Signed-off-by: Dmitry Osipenko 
Signed-off-by: Jonas Schwöbel 
Signed-off-by: Svyatoslav Ryhel 
Signed-off-by: Brian Masney

clk: tegra: clean-up simple provider misuse of the consumer API

2026-07-28T15:25:30+00:00

Clock provider should not be using the consumer interface.
In other words, a provider should not be dealing with struct clk.

This change targets occurrences for which the provider uses the
consumer interface and corresponding clk_hw interface exist.

Reviewed-by: Brian Masney 
Signed-off-by: Jerome Brunet 
Reviewed-by: Thierry Reding 
Signed-off-by: Brian Masney

clk: tegra: tegra124-emc: put EMC node on register failure

2026-07-28T15:25:29+00:00

tegra124_clk_register_emc() stores a device node reference returned by
of_parse_phandle() in tegra->emc_node.

If clk_register() fails, the function returns an error before that
reference can be consumed and released by the normal runtime path. The
tegra_clk_emc object is freed on this failure path, but freeing the
object does not drop the OF node reference stored in it.

Drop the EMC node reference before freeing the tegra_clk_emc object.
of_node_put() is safe for a NULL node, so this also covers the case where
the phandle is absent.

Fixes: 2db04f16b589 ("clk: tegra: Add EMC clock driver")
Signed-off-by: Guangshuo Li 
Reviewed-by: Brian Masney 
Signed-off-by: Brian Masney

Replace by more specific (c files)

2026-07-03T05:38:17+00:00

Replace the #include of  by the more specific
 where applicable. For most cases the include
can be dropped completely, only a few drivers need one or two headers
added.

Acked-by: Danilo Krummrich 
Acked-by: Takashi Sakamoto 
Acked-by: Bjorn Helgaas 
Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König (The Capable Hub)

clk: tegra: Support unique names for multi-socket platforms

2026-06-29T17:19:05+00:00

On multi-socket platforms each socket has its own BPMP which exposes the
same clock names. Fix this by using the NUMA ID as a prefix for the
clock names on multi-socket platforms.

Use 'sizeof(info->name)' in the strscpy() and snprintf() functions to
future proof against anyone changing the size of the 'name' array.

Co-developed-by: Timo Alho 
Signed-off-by: Timo Alho 
Signed-off-by: Jon Hunter 
Reviewed-by: Brian Masney 
Reviewed-by: Thierry Reding 
Signed-off-by: Brian Masney

Convert more 'alloc_obj' cases to default GFP_KERNEL arguments

2026-02-22T04:03:00+00:00

This converts some of the visually simpler cases that have been split
over multiple lines.  I only did the ones that are easy to verify the
resulting diff by having just that final GFP_KERNEL argument on the next
line.

Somebody should probably do a proper coccinelle script for this, but for
me the trivial script actually resulted in an assertion failure in the
middle of the script.  I probably had made it a bit _too_ trivial.

So after fighting that far a while I decided to just do some of the
syntactically simpler cases with variations of the previous 'sed'
scripts.

The more syntactically complex multi-line cases would mostly really want
whitespace cleanup anyway.

Signed-off-by: Linus Torvalds

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-22T01:09:51+00:00

This was done entirely with mindless brute force, using

    git grep -l '\