linux.git/drivers/clk/sunxi, branch v4.5

Merge tag 'sunxi-clocks-for-4.5' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

2015-12-24T07:23:18+00:00

Allwinner clocks changes for 4.5

Clock patches for the Allwinner SoCs:
  - H3 clocks
  - A10/A20 Video Engine clocks
  - DRAM gates
  - A80 special CPU clock

clk: sunxi: fix handling return value of of_property_match_string

2015-12-14T12:54:11+00:00

The function can return negative values, so its result should
be assigned to signed variable.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2046107

Signed-off-by: Andrzej Hajda 
Signed-off-by: Maxime Ripard

clk: sunxi: signedness bug in sun8i_h3_bus_gates_init()

2015-12-13T21:07:49+00:00

"index" needs to be signed for the error handling to work.

Fixes: ab6e23a4e388 ('clk: sunxi: Add H3 clocks support')
Signed-off-by: Dan Carpenter 
Signed-off-by: Maxime Ripard

clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver

2015-12-09T09:17:22+00:00

The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
instead of through a PRCM mfd device and subdevices for each clock
and reset control. As such we need a CLK_OF_DECLARE version of
the sun8i-a23-apb0-clk driver.

Also, build it for sun9i/A80, and not just for configurations with
MFD_SUN6I_PRCM enabled.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i

2015-12-08T10:05:27+00:00

The video engine has its own special module clock, consisting of a clock
gate, configurable dividers, and a reset control.

On later (sun[68]i) families, the reset control is moved out of this
piece of hardware and grouped with reset controls of other peripherals.

Signed-off-by: Chen-Yu Tsai 
Tested-by: Jens Kuske 
Signed-off-by: Maxime Ripard

clk: sunxi: Add H3 clocks support

2015-12-08T08:11:53+00:00

The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske 
Acked-by: Rob Herring 
Signed-off-by: Maxime Ripard

clk: sunxi: Add DRAM gates support for sun4i-a10

2015-12-07T08:58:17+00:00

The A10/A20 share the same set of DRAM clock gates, which controls
direct memory access for some peripherals.

On the A10, bit 15 controls the system's DRAM clock output (possibly
to the DRAM chips), which we need to keep on.

On the A20 this has been moved to the DRAM controller, becoming a no-op.
However it is still listed in the user manual, so add it anyway.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: pll2: Fix clock running too fast

2015-12-03T07:27:47+00:00

Contrary to what the datasheet says, the pre divider doesn't seem to be
incremented by one in the PLL2, but just uses the value from the register,
with 0 being a bypass.

This fixes the audio playing too fast.

Since we now have the same pre-divider flags, and the only difference with
the A10 is the post-divider offset, also remove the structure to just pass
the offset as an argument.

Signed-off-by: Maxime Ripard 
Fixes: eb662f854710 ("clk: sunxi: pll2: Add A13 support")
Signed-off-by: Stephen Boyd

clk: sunxi: Add sun9i A80 cpus (cpu special) clock support

2015-12-01T13:06:47+00:00

The "cpus" clock is the clock for the embedded processor in the A80.
It is also part of the PRCM clock tree. This clock includes a pre-
divider on one of its inputs. For now we are using a custom clock
driver for it. In the future we may want to develop a generalized
driver for these types of clocks, which also includes the AHB clock
driver on sun[5678]i.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
Signed-off-by: Maxime Ripard

clk: sunxi: Add sun9i A80 apbs gates support

2015-12-01T11:15:47+00:00

This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
Signed-off-by: Maxime Ripard