linux.git/drivers/clk/sunxi, branch v3.19

clk: Change clk_ops->determine_rate to return a clk_hw as the best parent

2014-12-04T00:21:37+00:00

This is in preparation for clock providers to not have to deal with struct clk.

Signed-off-by: Tomeu Vizoso 
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT mux

2014-11-23T16:02:57+00:00

A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk
has 2 bits selecting between 3 possible parents using values of 0, 1, 2,
which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in
its flag.

However we do not support parent 1 (an external clock), so use a table to
select parent 0 or 2, which are the 2 parents we support.

Note this has not been causing any issues sofar, because we start with a
parent setting of parent 0, and only ever re-parent to parent 2 (for which
we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set
we write a value of 2 for index 1.

Tested on both a cubietruck (which uses rgmii mode) as well as a cs908
(an a31s board which uses mii mode).

Signed-off-by: Hans de Goede 
Signed-off-by: Maxime Ripard

clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output

2014-11-23T16:02:56+00:00

Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
The first output will be the normal PLL6 output, and the second
will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes
any /2 dividers in the PLL6 factors clock part. The N factor counts
from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Specify number of child clocks for divs clocks

2014-11-23T16:02:56+00:00

Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.

On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names entry. This
results in an extra bogus clock being registered.

This patch adds an entry for the number of child clocks alongside
the data structures for them.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver

2014-11-23T16:02:56+00:00

This driver does not match the hardware, which is actually compatible
to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop
this driver.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: unify APB1 clock

2014-11-11T14:54:40+00:00

This commit unifies the APB1 mux with the APB1 clock, using the new
factors infrastructure.

Signed-off-by: Emilio López 
[wens@csie.org: Add mux mask bits]
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC

2014-10-21T19:47:34+00:00

This adds the gate clocks for AHB/APB busses on the A80 SoC.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Add support for A80 basic bus clocks

2014-10-21T19:45:48+00:00

The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new "GT" bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.

As far as I can tell, the GT bus and CCI400 bus clock must be
protected.

This patch adds driver support for peripheral related PLLs and
bus clocks on the A80. The GT and CCI400 clocks are added as well
as these 2 along with the PLLs they are clocked from must not be
disabled.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: make factors clock mux mask configurable

2014-10-21T19:40:56+00:00

Some of the factors-style clocks on the A80 have different widths
for the mux values in the registers.

Add a .muxmask field to clk_factors_config to make it configurable.
Passing a bitmask instead of a width parameter will allow reuse
in case we support table-based muxes in the future.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

2014-09-27T19:52:33+00:00

Allwinner Clocks Additions for 3.18

The most important part of this serie is the addition of the phase API to
handle the MMC clocks in the Allwinner SoCs.

Apart from that, the A23 gained a new mbus driver, and there's a fix for a
incorrect divider table on the APB0 clock.