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<title>linux.git/drivers/clk/sunxi, branch v3.17</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>clk: sunxi: staticize structures and arrays</title>
<updated>2014-07-28T22:39:22+00:00</updated>
<author>
<name>Emilio López</name>
<email>emilio@elopez.com.ar</email>
</author>
<published>2014-07-28T03:49:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=381c1ccd65f893fedfc608a907a1a06b73d98ca8'/>
<id>381c1ccd65f893fedfc608a907a1a06b73d98ca8</id>
<content type='text'>
There are some structs and arrays on the driver that are not used
anywhere else. Let's mark them as static.

Signed-off-by: Emilio López &lt;emilio@elopez.com.ar&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There are some structs and arrays on the driver that are not used
anywhere else. Let's mark them as static.

Signed-off-by: Emilio López &lt;emilio@elopez.com.ar&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: add __iomem markings to MMIO pointers</title>
<updated>2014-07-28T22:39:05+00:00</updated>
<author>
<name>Emilio López</name>
<email>emilio@elopez.com.ar</email>
</author>
<published>2014-07-28T03:49:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=89a9456d6ecdf328a66a561a43e9bdc3c2a2208d'/>
<id>89a9456d6ecdf328a66a561a43e9bdc3c2a2208d</id>
<content type='text'>
This commit adds __iomem thoughout the sunxi clock driver, in places
where it was ommited. This cleans most of the sparse warnings we
are getting here.

Signed-off-by: Emilio López &lt;emilio@elopez.com.ar&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This commit adds __iomem thoughout the sunxi clock driver, in places
where it was ommited. This cleans most of the sparse warnings we
are getting here.

Signed-off-by: Emilio López &lt;emilio@elopez.com.ar&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next-sunxi</title>
<updated>2014-07-26T00:45:30+00:00</updated>
<author>
<name>Mike Turquette</name>
<email>mturquette@linaro.org</email>
</author>
<published>2014-07-26T00:45:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3cc5aba4158e757ddd33751db6ca1729741e8dba'/>
<id>3cc5aba4158e757ddd33751db6ca1729741e8dba</id>
<content type='text'>
Allwinner clocks additions for 3.17

This pull request adds support for the clocks found in the newly supported
Allwinner A23 clocks.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allwinner clocks additions for 3.17

This pull request adds support for the clocks found in the newly supported
Allwinner A23 clocks.
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support</title>
<updated>2014-07-15T06:53:24+00:00</updated>
<author>
<name>Chen-Yu Tsai</name>
<email>wens@csie.org</email>
</author>
<published>2014-07-09T07:54:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6c1d66f0da59362cb33ce37d436cd28c77c2b2cb'/>
<id>6c1d66f0da59362cb33ce37d436cd28c77c2b2cb</id>
<content type='text'>
This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific
compatible to the sun6i-a31-apb0-gates clock driver, along with the
gate bitmap.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific
compatible to the sun6i-a31-apb0-gates clock driver, along with the
gate bitmap.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indices</title>
<updated>2014-07-15T06:52:11+00:00</updated>
<author>
<name>Chen-Yu Tsai</name>
<email>wens@csie.org</email>
</author>
<published>2014-07-09T07:54:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b72efd0f651271ee05835ab848eee7c4e6851c99'/>
<id>b72efd0f651271ee05835ab848eee7c4e6851c99</id>
<content type='text'>
sun6i-apb0-gates uses the "clock-indices" DT property to indicate
valid gate bits or holes in between. However, the rest of sunxi
clock drivers use bitmaps for this purpose.

This patch modifies sun6i-apb0-gates to use bitmaps as well, to be
consistent with the sunxi platform. Also add the missing call to
clk_register_clkdev, so system clock lookups will work.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
sun6i-apb0-gates uses the "clock-indices" DT property to indicate
valid gate bits or holes in between. However, the rest of sunxi
clock drivers use bitmaps for this purpose.

This patch modifies sun6i-apb0-gates to use bitmaps as well, to be
consistent with the sunxi platform. Also add the missing call to
clk_register_clkdev, so system clock lookups will work.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates</title>
<updated>2014-07-07T08:53:52+00:00</updated>
<author>
<name>Chen-Yu Tsai</name>
<email>wens@csie.org</email>
</author>
<published>2014-07-03T14:55:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=cd6eb534fbb8c9c52e6900f6b086d8c95f966449'/>
<id>cd6eb534fbb8c9c52e6900f6b086d8c95f966449</id>
<content type='text'>
sun6i-a31-apb0-gates supports using clock-indices for holes between
individual gates. However, the driver passes the number of gates
registered in clk_data-&gt;clk_num, which of_clk_src_onecell_get uses
to recognize the range of valid indices a consumer can use.

This patch makes the driver pass the maximum gate index + 1, so
of_clk_src_onecell_get does not complain about indices greater
than gates registered.

This was tested on the A23 SoC, which has a similar APB0 clock,
but has holes for gates to removed IP blocks.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
sun6i-a31-apb0-gates supports using clock-indices for holes between
individual gates. However, the driver passes the number of gates
registered in clk_data-&gt;clk_num, which of_clk_src_onecell_get uses
to recognize the range of valid indices a consumer can use.

This patch makes the driver pass the maximum gate index + 1, so
of_clk_src_onecell_get does not complain about indices greater
than gates registered.

This was tested on the A23 SoC, which has a similar APB0 clock,
but has holes for gates to removed IP blocks.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: Add A23 APB0 divider clock support</title>
<updated>2014-07-07T08:46:21+00:00</updated>
<author>
<name>Chen-Yu Tsai</name>
<email>wens@csie.org</email>
</author>
<published>2014-07-03T14:55:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=57a1fbf28424561a080b34fbdd04661282aea40e'/>
<id>57a1fbf28424561a080b34fbdd04661282aea40e</id>
<content type='text'>
The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.

This patch adds a separate sun8i-a23-apb0-clk driver to support it.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.

This patch adds a separate sun8i-a23-apb0-clk driver to support it.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: Add A23 clocks support</title>
<updated>2014-07-04T10:05:17+00:00</updated>
<author>
<name>Chen-Yu Tsai</name>
<email>wens@csie.org</email>
</author>
<published>2014-06-26T15:55:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=515c1a4bdcd9b55e2c21e897a9ca276bd708d145'/>
<id>515c1a4bdcd9b55e2c21e897a9ca276bd708d145</id>
<content type='text'>
The clock control unit on the A23 is similar to the one found on the A31.

The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.

The main CPU PLL (PLL1) however is like that on older Allwinner SoCs,
such as the A10 or A20, but the N factor starts from 1 instead of 0.

This patch adds support for PLL1 and all the basic clock muxes and gates.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The clock control unit on the A23 is similar to the one found on the A31.

The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.

The main CPU PLL (PLL1) however is like that on older Allwinner SoCs,
such as the A10 or A20, but the N factor starts from 1 instead of 0.

This patch adds support for PLL1 and all the basic clock muxes and gates.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: Add support for table-based divider clocks</title>
<updated>2014-07-04T10:05:13+00:00</updated>
<author>
<name>Chen-Yu Tsai</name>
<email>wens@csie.org</email>
</author>
<published>2014-06-26T15:55:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ea5671bffbb2b6eefdce7e467a162ae2eef032ac'/>
<id>ea5671bffbb2b6eefdce7e467a162ae2eef032ac</id>
<content type='text'>
A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.

This patch adds support for optional divider tables,
so the clock framework will know about the odd values.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.

This patch adds support for optional divider tables,
so the clock framework will know about the odd values.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: Support factor clocks with N factor starting not from 0</title>
<updated>2014-07-04T10:05:12+00:00</updated>
<author>
<name>Chen-Yu Tsai</name>
<email>wens@csie.org</email>
</author>
<published>2014-06-26T15:55:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=9a5e6c7eb5ccbb5f0d3a1dffce135f0a727f40e1'/>
<id>9a5e6c7eb5ccbb5f0d3a1dffce135f0a727f40e1</id>
<content type='text'>
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.

This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.

This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
