linux.git/drivers/clk/sunxi, branch v3.15

clk: sunxi: fix thinko in comment

2014-03-19T19:35:07+00:00

This should read MOD0 and not MMC; MMC is just one example of a MOD0
clock.

Signed-off-by: Emilio López 
Signed-off-by: Mike Turquette

clk: sunxi: fix some calculations

2014-03-19T19:34:56+00:00

Some divisor calculations were misrounded, causing higher than requested
rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one
homebrew instance of it as well with the right macro.

Reported-by: Boris BREZILLON 
Signed-off-by: Emilio López 
Signed-off-by: Mike Turquette

clk: sunxi: fix A20 PLL4 calculation

2014-03-19T19:34:39+00:00

Allwinner actually reworked the PLL4 on A20; now it's compatible with
the sun4i PLL5/6 design previous to any divisions, as well as to the new
PLL8 in sun7i.

Signed-off-by: Emilio López 
Signed-off-by: Mike Turquette

clk: sunxi: Add new clock compatibles

2014-02-18T13:34:28+00:00

The Allwinner A10 compatibles were following a slightly different compatible
patterns than the rest of the SoCs for historical reasons. Add compatibles
matching the other pattern to the clock driver for consistency, and keep the
older one for backward compatibility.

Signed-off-by: Maxime Ripard 
Signed-off-by: Emilio López

clk: sunxi: Add Allwinner A20/A31 GMAC clock unit

2014-02-18T13:34:28+00:00

The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Signed-off-by: Emilio López

clk: sunxi: Add support for PLL6 on the A31

2014-02-18T12:45:13+00:00

The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.

Signed-off-by: Maxime Ripard 
Signed-off-by: Emilio López

clk: sunxi: Add USB clock register defintions

2014-02-18T12:35:20+00:00

Add register definitions for the usb-clk register found on sun4i, sun5i and
sun7i SoCs.

Signed-off-by: Roman Byshko 
Signed-off-by: Hans de Goede 
Acked-by: Maxime Ripard 
Signed-off-by: Emilio López

clk: sunxi: Add support for USB clock-register reset bits

2014-02-18T12:29:10+00:00

The usb-clk register is special in that it not only contains clk gate bits,
but also has a few reset bits. This commit adds support for this by allowing
gates type sunxi clks to also register a reset controller.

Signed-off-by: Hans de Goede 
Acked-by: Philipp Zabel 
Acked-by: Maxime Ripard 
Signed-off-by: Emilio López

clk: sunxi: get divs parent clock name from parent factor clock

2014-02-03T03:24:33+00:00

Divs clocks consist of a parent factor clock with multiple outputs,
and seperate clocks for each output. Get the name of the parent
clock from the parent factor clock, instead of the DT node name.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Acked-by: Mike Turquette 
Signed-off-by: Emilio López

clk: sunxi: add names for pll5, pll6 parent clocks to factors_data

2014-02-03T03:24:32+00:00

Some factor clocks, such as the parent clock of pll5 and pll6, have
multiple output names. Add the corresponding names to factors_data
tied to compatible string.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Acked-by: Mike Turquette 
Signed-off-by: Emilio López