linux.git/drivers/clk/sunxi, branch v3.14

clk: sunxi: fix overflow when setting up divided factors

2014-01-27T20:28:23+00:00

Currently, we are allocating space for two pointers, when we actually
may need to store three of them (two divisors plus the original clock).
Fix this, and change sizeof(type) to sizeof(*var) to keep checkpatch.pl
happy.

Reported-by: Dan Carpenter 
Signed-off-by: Emilio López 
Signed-off-by: Mike Turquette

clk: sunxi: Allwinner A20 output clock support

2013-12-28T20:14:21+00:00

This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Emilio López

clk: sunxi: support better factor DT nodes

2013-12-28T20:08:25+00:00

The DT nodes should look like

    abc_clk: clk@deadbeef {
        ...
        clock-output-names = "abc";
    }

But our old DT nodes look like

    abc: abc@deadbeef {
        ...
    }

So, let's support both formats, until we can transition everything
to the new, correct one.

Signed-off-by: Emilio López 
Acked-by: Mike Turquette

clk: sunxi: mod0 support

2013-12-28T20:08:22+00:00

This commit implements support for the "module 0" type of clocks, as
used by MMC, IR, NAND, SATA and other components.

Signed-off-by: Emilio López 
Acked-by: Mike Turquette

clk: sunxi: add PLL5 and PLL6 support

2013-12-28T20:08:17+00:00

This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.

Signed-off-by: Emilio López 
Acked-by: Mike Turquette

clk: sunxi: make factors_clk_setup return the clock it registers

2013-12-28T20:08:14+00:00

We will be needing this to register a factor clock as parent with leaf
divisors on a single call.

Signed-off-by: Emilio López 
Acked-by: Mike Turquette

clk: sunxi: add gating support to PLL1

2013-12-28T20:08:06+00:00

This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.

Signed-off-by: Emilio López 
Acked-by: Maxime Ripard 
Acked-by: Mike Turquette

clk: sunxi: clean the magic number of mux parents

2013-12-28T20:08:00+00:00

This was pointed out during the review of the factor patches. Let's
indicate what does that magic 5 mean.

Signed-off-by: Emilio López 
Acked-by: Mike Turquette

clk: sunxi: register factors clocks behind composite

2013-12-28T20:07:42+00:00

This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.

Signed-off-by: Emilio López 
Acked-by: Maxime Ripard 
Acked-by: Mike Turquette

Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-next-sunxi-rebase

2013-12-01T20:42:45+00:00

Allwinner sunXi SoCs clock changes

Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.

Conflicts:
	drivers/clk/sunxi/clk-sunxi.c