linux.git/drivers/clk/shmobile, branch v3.15

clk: shmobile: clk-mstp: change to using clock-indices

2014-05-12T23:53:37+00:00

With the addition of clock-indices, we need to change the renesas
clock implementation to use these instead of the local definition
of "renesas,clock-indices".

Since this will break booting with older device trees, we add a
simple auto-detection of which properties are present.

Signed-off-by: Ben Dooks 
Acked-by: Geert Uytterhoeven 
Reviewed-by: Wolfram Sang 
Signed-off-by: Mike Turquette

Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux

2014-04-06T01:39:18+00:00

Pull clock framework changes from Mike Turquette:
 "The clock framework changes for 3.15 look similar to past pull
  requests.  Mostly clock driver updates, more Device Tree support in
  the form of common functions useful across platforms and a handful of
  features and fixes to the framework core"

* tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: shmobile: fix setting paretn clock rate
  clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
  clk: Fix minor errors in of_clk_init() function comments
  clk: reverse default clk provider initialization order in of_clk_init()
  clk: sirf: update copyright years to 2014
  clk: mmp: try to use closer one when do round rate
  clk: mmp: fix the wrong calculation formula
  clk: mmp: fix wrong mask when calculate denominator
  clk: st: Adds quadfs clock binding
  clk: st: Adds clockgen-vcc and clockgen-mux clock binding
  clk: st: Adds clockgen clock binding
  clk: st: Adds divmux and prediv clock binding
  clk: st: Support for A9 MUX clocks
  clk: st: Support for ClockGenA9/DDR/GPU
  clk: st: Support for QUADFS inside ClockGenB/C/D/E/F
  clk: st: Support for VCC-mux and MUX clocks
  clk: st: Support for PLLs inside ClockGenA(s)
  clk: st: Support for DIVMUX and PreDiv Clocks
  clk: support hardware-specific debugfs entries
  clk: s2mps11: Use of_get_child_by_name
  ...

clk: shmobile: fix setting paretn clock rate

2014-04-02T18:31:05+00:00

If the driver needs to change a clock rate, then it must be propogated
through the MSTP clock to the parent clock (such as shdi0 -> sd0). Without
this we cannot up-rate default clocks which are really slow (such as the
mmcif1 which defaults to 12MHz where it could be running at 97MHz)

Signed-off-by: Ben Dooks 
Acked-by: Laurent Pinchart 
Signed-off-by: Mike Turquette

clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1

2014-04-01T00:06:28+00:00

The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks
parented to pll1_div2 where the hardware diagram shows these to be
directly fed from pll1.

This fixes the initial rate for sdh0 clock to be 97.5MHz instead of
the reported 48MHz where the manual says the default register values
are for 97.5MHz.

Signed-off-by: Ben Dooks 
Acked-by: Laurent Pinchart 
Signed-off-by: Mike Turquette

clk: shmobile: add CPG driver for rz-platforms

2014-03-21T01:22:36+00:00

Signed-off-by: Wolfram Sang 
Signed-off-by: Mike Turquette

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux

2014-03-08T18:51:30+00:00

Pull clk driver fix from Mike Turquette:
 "Single fix for a clock driver merged in 3.14-rc1.  Without this fix
  the CPU frequency cannot be scaled"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
  clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change

clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change

2014-03-06T06:41:15+00:00

The Z clock frequency change is effective only after setting the kick
bit located in the FRQCRB register.
Without that, the CA15 CPUs clock rate will never change.

Fix that by checking if the kick bit is cleared and enable it to make
the clock rate change effective. The bit is cleared automatically upon
completion.

Signed-off-by: Benoit Cousson 
Acked-by: Laurent Pinchart 
Signed-off-by: Mike Turquette

clk: shmobile: div6: use proper description in kernel doc

2014-02-25T08:26:37+00:00

These variable clocks have nothing to do with MSTP gating, probably a
copy&paste leftover.

Signed-off-by: Wolfram Sang 
Acked-by: Laurent Pinchart 
Signed-off-by: Mike Turquette

clk: shmobile: rcar-gen2: Fix qspi divisor

2014-02-19T05:41:03+00:00

The qspi clock divisor is incorrectly set to twice the value it should
have, possibly because it has been computed based on PLL1 as the clock
parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal
frequencies, not the divisor values). Fix it.

Reported-by: Geert Uytterhoeven 
Signed-off-by: Laurent Pinchart 
Tested-by: Geert Uytterhoeven 
Acked-by: Simon Horman 
Signed-off-by: Mike Turquette

clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks

2014-02-19T05:41:01+00:00

The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as
their parent, not the main clock. Fix it.

Reported-by: Geert Uytterhoeven 
Signed-off-by: Laurent Pinchart 
Tested-by: Geert Uytterhoeven 
Acked-by: Simon Horman 
Signed-off-by: Mike Turquette