linux.git/drivers/clk/rockchip, branch v6.5 Linux kernel source tree Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next 2023-04-25T18:52:25+00:00 Stephen Boyd sboyd@kernel.org 2023-04-25T18:52:25+00:00 c19c6c7b44c69faa7a18ef79e758f580b144fd8f * clk-of: clk: add missing of_node_put() in "assigned-clocks" property parsing * clk-samsung: clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical clk: samsung: Convert to platform remove callback returning void clk: samsung: exynos5433: Extract PM support to common ARM64 layer clk: samsung: Extract parent clock enabling to common function clk: samsung: Extract clocks registration to common function clk: samsung: exynos850: Add AUD and HSI main gate clocks clk: samsung: exynos850: Implement CMU_G3D domain clk: samsung: clk-pll: Implement pll0818x PLL type clk: samsung: Set dev in samsung_clk_init() clk: samsung: Don't pass reg_base to samsung_clk_register_pll() clk: samsung: Remove np argument from samsung_clk_init() dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D * clk-rockchip: clk: rockchip: rk3588: make gate linked clocks critical clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent * clk-qcom: (57 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: qcom: Add Global Clock Controller driver for IPQ9574 dt-bindings: clock: Add ipq9574 clock and reset definitions clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value clk: qcom: gcc-sm6115: Mark RCGs shared where applicable clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset clk: qcom: apss-ipq-pll: add support for IPQ5332 dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks ... 
* clk-of:
  clk: add missing of_node_put() in "assigned-clocks" property parsing

* clk-samsung:
  clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical
  clk: samsung: Convert to platform remove callback returning void
  clk: samsung: exynos5433: Extract PM support to common ARM64 layer
  clk: samsung: Extract parent clock enabling to common function
  clk: samsung: Extract clocks registration to common function
  clk: samsung: exynos850: Add AUD and HSI main gate clocks
  clk: samsung: exynos850: Implement CMU_G3D domain
  clk: samsung: clk-pll: Implement pll0818x PLL type
  clk: samsung: Set dev in samsung_clk_init()
  clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
  clk: samsung: Remove np argument from samsung_clk_init()
  dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
  dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D

* clk-rockchip:
  clk: rockchip: rk3588: make gate linked clocks critical
  clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent

* clk-qcom: (57 commits)
  clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
  clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
  clk: qcom: add the GPUCC driver for sa8775p
  dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
  clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
  clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
  clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
  dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
  clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
  clk: qcom: Add Global Clock Controller driver for IPQ9574
  dt-bindings: clock: Add ipq9574 clock and reset definitions
  clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
  clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
  clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
  dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
  clk: qcom: apss-ipq-pll: add support for IPQ5332
  dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
  clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
  dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
  dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
  ...
clk: rockchip: rk3588: make gate linked clocks critical 2023-04-17T22:54:04+00:00 Sebastian Reichel sebastian.reichel@collabora.com 2023-04-03T19:32:49+00:00 64042c28c3bb6729df8e2fda89bc7ebbe3790907 RK3588 has a couple of hardware blocks called Native Interface Unit (NIU) that gate the clocks to devices behind them. Effectively this means that some clocks require two parent clocks being enabled. Downstream implemented this by using a separate clock driver ("clk-link") for them, which enables the second clock using PM framework. In the upstream kernel we are currently missing support for the second parent. The information about it is in the GATE_LINK() macro as linkname, but that is not used. Thus the second parent clock is not properly enabled. So far this did not really matter, since these clocks are mostly required for the more advanced IP blocks, that are not yet supported upstream. As this is about to change we need a fix. There are three options available: 1. Properly implement support for having two parent clocks in the clock framework. 2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not disabled. This wastes some power, but keeps the hack contained within the clock driver. Going from this to the first solution is easy once that has been implemented. 3. Enabling the extra clock in the consumer driver. This leaks some implementation details into DT. This patch implements the second option as an intermediate solution until the first one is available. I used an alias for CLK_IS_CRITICAL, so that it's easy to see which clocks are not really critical once the clock framework supports a better way to implement this. Tested-by: Vincent Legoll <vincent.legoll@gmail.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230403193250.108693-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 
RK3588 has a couple of hardware blocks called Native Interface Unit
(NIU) that gate the clocks to devices behind them. Effectively this
means that some clocks require two parent clocks being enabled.
Downstream implemented this by using a separate clock driver
("clk-link") for them, which enables the second clock using PM
framework.

In the upstream kernel we are currently missing support for the second
parent. The information about it is in the GATE_LINK() macro as
linkname, but that is not used. Thus the second parent clock is not
properly enabled. So far this did not really matter, since these clocks
are mostly required for the more advanced IP blocks, that are not yet
supported upstream. As this is about to change we need a fix. There
are three options available:

1. Properly implement support for having two parent clocks in the
   clock framework.
2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
   disabled. This wastes some power, but keeps the hack contained
   within the clock driver. Going from this to the first solution
   is easy once that has been implemented.
3. Enabling the extra clock in the consumer driver. This leaks some
   implementation details into DT.

This patch implements the second option as an intermediate solution
until the first one is available. I used an alias for CLK_IS_CRITICAL,
so that it's easy to see which clocks are not really critical once
the clock framework supports a better way to implement this.

Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230403193250.108693-2-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_divider 2023-04-05T19:09:27+00:00 Christophe JAILLET christophe.jaillet@wanadoo.fr 2023-04-02T09:42:06+00:00 645a5198ddba6d6b2dea8346ca796064e931a0c3 Now that fractional_divider clk computes mmask and nmask when needed, there is no more need to provide them explicitly anymore. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/58e1950566e40e2fbb31004baee57a164ca6a390.1680423909.git.christophe.jaillet@wanadoo.fr Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Now that fractional_divider clk computes mmask and nmask when needed, there
is no more need to provide them explicitly anymore.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/58e1950566e40e2fbb31004baee57a164ca6a390.1680423909.git.christophe.jaillet@wanadoo.fr
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent 2023-03-07T10:26:27+00:00 Quentin Schulz quentin.schulz@theobroma-systems.com 2022-11-17T12:04:31+00:00 933bf364e152cd60902cf9585c2ba310d593e69f clk_cifout is derived from clk_cifout_src through an integer divider limited to 32. clk_cifout_src is a child of either cpll, gpll or npll without any possibility of a divider of any sort. The default clock parent is cpll. Let's allow clk_cifout to ask its parent clk_cifout_src to reparent in order to find the real closest possible rate for clk_cifout and not one derived from cpll only. Cc: stable@vger.kernel.org # 4.10+ Fixes: fd8bc829336a ("clk: rockchip: fix the rk3399 cifout clock") Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20221117-rk3399-cifout-set-rate-parent-v1-0-432548d04081@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 
clk_cifout is derived from clk_cifout_src through an integer divider
limited to 32. clk_cifout_src is a child of either cpll, gpll or npll
without any possibility of a divider of any sort. The default clock
parent is cpll.

Let's allow clk_cifout to ask its parent clk_cifout_src to reparent in
order to find the real closest possible rate for clk_cifout and not one
derived from cpll only.

Cc: stable@vger.kernel.org # 4.10+
Fixes: fd8bc829336a ("clk: rockchip: fix the rk3399 cifout clock")
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/r/20221117-rk3399-cifout-set-rate-parent-v1-0-432548d04081@theobroma-systems.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Merge branches 'clk-spear', 'clk-fract', 'clk-rockchip' and 'clk-imx' into clk-next 2022-12-12T19:13:08+00:00 Stephen Boyd sboyd@kernel.org 2022-12-12T19:13:08+00:00 e0a1d1394b220d8083c773d1f208925aa1e0eddf - Debugfs support for fractional divider clk * clk-spear: clk: spear: Fix SSP clock definition on SPEAr600 clk: spear: Fix CLCD clock definition on SPEAr600 * clk-fract: clk: fractional-divider: Regroup inclusions clk: fractional-divider: Show numerator and denominator in debugfs clk: fractional-divider: Split out clk_fd_get_div() helper * clk-rockchip: clk: rockchip: Fix memory leak in rockchip_clk_register_pll() clk: rockchip: add clock controller for the RK3588 clk: rockchip: add lookup table support clk: rockchip: simplify rockchip_clk_add_lookup clk: rockchip: allow additional mux options for cpu-clock frequency changes clk: rockchip: add pll type for RK3588 clk: rockchip: add register offset of the cores select parent dt-bindings: clock: add rk3588 cru bindings dt-bindings: reset: add rk3588 reset definitions dt-bindings: clock: add rk3588 clock definitions clk: rockchip: use proper crypto0 name on rk3399 * clk-imx: clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name() clk: imx8mn: fix imx8mn_enet_phy_sels clocks list clk: imx8mn: fix imx8mn_sai2_sels clocks list clk: imx: rename video_pll1 to video_pll clk: imx: replace osc_hdmi with dummy clk: imx8mn: rename vpu_pll to m7_alt_pll clk: imx: imxrt1050: add IMXRT1050_CLK_LCDIF_PIX clock gate clk: imx: imxrt1050: fix IMXRT1050_CLK_LCDIF_APB offsets clk: imx8mp: Add audio shared gate dt-bindings: clock: imx8mp: Add ids for the audio shared gate clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x clk: imx93: keep sys ctr clock always on clk: imx: keep hsio bus clock always on clk: imx93: drop tpm1/3, lpit1/2 clk dt-bindings: clock: imx93: drop TPM1/3 LPIT1/2 entry clk: imx93: correct enet clock clk: imx93: unmap anatop base in error handling path clk: imx: imx8mp: add shared clk gate for usb suspend clk dt-bindings: clocks: imx8mp: Add ID for usb suspend clock clk: imx93: correct the flexspi1 clock setting 
 - Debugfs support for fractional divider clk

* clk-spear:
  clk: spear: Fix SSP clock definition on SPEAr600
  clk: spear: Fix CLCD clock definition on SPEAr600

* clk-fract:
  clk: fractional-divider: Regroup inclusions
  clk: fractional-divider: Show numerator and denominator in debugfs
  clk: fractional-divider: Split out clk_fd_get_div() helper

* clk-rockchip:
  clk: rockchip: Fix memory leak in rockchip_clk_register_pll()
  clk: rockchip: add clock controller for the RK3588
  clk: rockchip: add lookup table support
  clk: rockchip: simplify rockchip_clk_add_lookup
  clk: rockchip: allow additional mux options for cpu-clock frequency changes
  clk: rockchip: add pll type for RK3588
  clk: rockchip: add register offset of the cores select parent
  dt-bindings: clock: add rk3588 cru bindings
  dt-bindings: reset: add rk3588 reset definitions
  dt-bindings: clock: add rk3588 clock definitions
  clk: rockchip: use proper crypto0 name on rk3399

* clk-imx:
  clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()
  clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
  clk: imx8mn: fix imx8mn_sai2_sels clocks list
  clk: imx: rename video_pll1 to video_pll
  clk: imx: replace osc_hdmi with dummy
  clk: imx8mn: rename vpu_pll to m7_alt_pll
  clk: imx: imxrt1050: add IMXRT1050_CLK_LCDIF_PIX clock gate
  clk: imx: imxrt1050: fix IMXRT1050_CLK_LCDIF_APB offsets
  clk: imx8mp: Add audio shared gate
  dt-bindings: clock: imx8mp: Add ids for the audio shared gate
  clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x
  clk: imx93: keep sys ctr clock always on
  clk: imx: keep hsio bus clock always on
  clk: imx93: drop tpm1/3, lpit1/2 clk
  dt-bindings: clock: imx93: drop TPM1/3 LPIT1/2 entry
  clk: imx93: correct enet clock
  clk: imx93: unmap anatop base in error handling path
  clk: imx: imx8mp: add shared clk gate for usb suspend clk
  dt-bindings: clocks: imx8mp: Add ID for usb suspend clock
  clk: imx93: correct the flexspi1 clock setting
clk: rockchip: Fix memory leak in rockchip_clk_register_pll() 2022-11-23T13:51:30+00:00 Xiu Jianfeng xiujianfeng@huawei.com 2022-11-23T09:12:01+00:00 739a6a6bbdb793bd57938cb24aa5a6df89983546 If clk_register() fails, @pll->rate_table may have allocated memory by kmemdup(), so it needs to be freed, otherwise will cause memory leak issue, this patch fixes it. Fixes: 90c590254051 ("clk: rockchip: add clock type for pll clocks and pll used on rk3066") Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com> Link: https://lore.kernel.org/r/20221123091201.199819-1-xiujianfeng@huawei.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 
If clk_register() fails, @pll->rate_table may have allocated memory by
kmemdup(), so it needs to be freed, otherwise will cause memory leak
issue, this patch fixes it.

Fixes: 90c590254051 ("clk: rockchip: add clock type for pll clocks and pll used on rk3066")
Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Link: https://lore.kernel.org/r/20221123091201.199819-1-xiujianfeng@huawei.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: Remove a useless include 2022-11-23T01:52:07+00:00 Christophe JAILLET christophe.jaillet@wanadoo.fr 2022-11-12T21:43:03+00:00 12897adc8eea9e56e44482dcdf71d4c98a08dbde <linux/rational.h> is not needed for these drivers. Remove the corresponding #include. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/12dd5cb49efa7714f8e0389e4c7b3bc829e8a90e.1668289299.git.christophe.jaillet@wanadoo.fr Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
<linux/rational.h> is not needed for these drivers. Remove the
corresponding #include.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/12dd5cb49efa7714f8e0389e4c7b3bc829e8a90e.1668289299.git.christophe.jaillet@wanadoo.fr
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: rockchip: add clock controller for the RK3588 2022-11-15T10:37:41+00:00 Elaine Zhang zhangqing@rock-chips.com 2022-10-18T15:14:07+00:00 f1c506d152ff235ad621d3c25d061cb16da67214 Add full clock controller support RK3588. [rebase, integrate fixes from Wyon and Finley, add missing frequencies to PLL lookup table, update commit message, add GATE_LINK clocks which downstream handles in its own driver with one DT node per clock] Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com [dropped module stuff after talking to Sebastian] Signed-off-by: Heiko Stuebner <heiko@sntech.de> 
Add full clock controller support RK3588.

[rebase, integrate fixes from Wyon and Finley, add missing frequencies
 to PLL lookup table, update commit message, add GATE_LINK clocks which
 downstream handles in its own driver with one DT node per clock]

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com
[dropped module stuff after talking to Sebastian]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: rockchip: add lookup table support 2022-11-14T14:35:07+00:00 Sebastian Reichel sebastian.reichel@collabora.com 2022-10-18T15:14:06+00:00 ada8f95ba04e8fe07289b7de157ae99bb96bc8cb Add support for mapping reset IDs to register offsets to support gapless continous platform reset IDs. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 
Add support for mapping reset IDs to register offsets
to support gapless continous platform reset IDs.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: rockchip: simplify rockchip_clk_add_lookup 2022-11-14T14:35:07+00:00 Sebastian Reichel sebastian.reichel@collabora.com 2022-10-18T15:14:05+00:00 ff94c8660dac444081f2f650fae36a283c55b117 rockchip_clk_add_lookup is only called from within the file, so it can be made static. The additional checks are removed with the following reasoning: 1. The data structure is initialized by rockchip_clk_init(), which is called by all rockchip platforms before the clocks are registered. Not doing so would result in an incomplete clock tree at the moment, which is a fatal error. In other parts of the kernel these kind of checks are usually omitted, so this was done here. The alternative is adding a pr_err to inform the kernel programmer adding a new platform about his incorrect code. Apart from that we are also not checking if the clock id is within the array boundings. 2. While not used so far by any rockchip platform, 0 is a valid clock identifier. To align rockchip closer to other ARM platforms we will start using it with rk3588. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 
rockchip_clk_add_lookup is only called from within the file,
so it can be made static. The additional checks are removed
with the following reasoning:

1. The data structure is initialized by rockchip_clk_init(),
   which is called by all rockchip platforms before the clocks
   are registered. Not doing so would result in an incomplete
   clock tree at the moment, which is a fatal error. In other
   parts of the kernel these kind of checks are usually
   omitted, so this was done here. The alternative is adding
   a pr_err to inform the kernel programmer adding a new platform
   about his incorrect code. Apart from that we are also not
   checking if the clock id is within the array boundings.

2. While not used so far by any rockchip platform, 0 is a valid
   clock identifier. To align rockchip closer to other ARM
   platforms we will start using it with rk3588.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>