linux.git/drivers/clk/rockchip, branch v5.8

clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocks

2020-04-13T07:35:24+00:00

The following changes prevent the unrecoverable freezes and rcu_sched
stall warnings experienced in each of my attempts to take advantage of
lima.

Replace the COMPOSITE_NOGATE definition of aclk_gpu_pre with a
COMPOSITE that retains the selection of HDMIPHY as the PLL source, but
instead makes uses of the aclk_gpu PLL source gate and parent names
defined by mux_pll_src_4plls_p rather than mux_aclk_gpu_pre_p.

Remove the now unused mux_aclk_gpu_pre_p and the four named but also
unused definitions (cpll_gpu, gpll_gpu, hdmiphy_gpu and usb480m_gpu)
of the aclk_gpu PLL source gate.

Use the correct gate offset for aclk_gpu and aclk_gpu_noc.

Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
Cc: stable@vger.kernel.org
Signed-off-by: Justin Swartz 
[double-checked against SoC manual and added fixes tag]
Link: https://lore.kernel.org/r/20200114162503.7548-1-justin.swartz@risingedge.co.za
Signed-off-by: Heiko Stuebner

clk: rockchip: fix mmc get phase

2020-03-06T20:06:01+00:00

If the mmc clock has no rate, it can be assumed to be constant.
In such case, there is no measurable phase shift. Just return 0
in this case instead of returning an error.

Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration")
Tested-by: Markus Reichl 
Signed-off-by: Jerome Brunet 
Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd

clk: let init callback return an error code

2019-12-24T02:53:13+00:00

If the init callback is allowed to request resources, it needs a return
value to report the outcome of such a request.

Signed-off-by: Jerome Brunet 
Link: https://lkml.kernel.org/r/20190924123954.31561-3-jbrunet@baylibre.com
Reviewed-by: Andrew Lunn 
Acked-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd

clk: rockchip: protect the pclk_usb_grf as critical on px30

2019-11-05T19:53:42+00:00

Make this clock a real critical clock, so that writes to the usbphy grf
always succeed.

Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20190917081903.25139-5-heiko@sntech.de

clk: rockchip: add video-related niu clocks as critical on px30

2019-11-05T19:53:39+00:00

Video-In and -Out interconnect clocks need to stay on all the
time for the peripheral to work and we do not model the actual
interconnect at this point. So mark them as critical for now.

Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20190917081903.25139-4-heiko@sntech.de

clk: rockchip: move px30 critical clocks to correct clock controller

2019-11-05T19:53:34+00:00

The clocks in the px30 critical clock section are from the regular cru not
the pmucru, so move them to the correct place.

Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20190917081903.25139-3-heiko@sntech.de

clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc

2019-11-05T19:53:30+00:00

Some IPs, such as NAND, EMMC, SDIO and SDMMC need clock of 50%  duty
cycle, divfree50 can generate clock of 50% duty cycle even in odd
value divisor.

Signed-off-by: Finley Xiao 
Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20190917081903.25139-2-heiko@sntech.de

clk: rockchip: make clk_half_divider_ops static

2019-10-31T11:06:01+00:00

The clk_half_divider_ops is not used outside or declared
outside of drivers/clk/rockchip/clk-half-divider.c so make
it static to avoid the following warning:

drivers/clk/rockchip/clk-half-divider.c:142:22: warning: symbol 'clk_half_divider_ops' was not declared. Should it be static?

Signed-off-by: Ben Dooks 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20191017105348.8061-1-ben.dooks@codethink.co.uk
Signed-off-by: Heiko Stuebner

clk: rockchip: Add clock controller for the rk3308

2019-09-05T10:43:39+00:00

Add the clock tree definition for the new RK3308 SoC.

Signed-off-by: Finley Xiao 
Signed-off-by: Heiko Stuebner

clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver

2019-07-25T19:00:52+00:00

Clang produces the following warning

drivers/clk/rockchip/clk-rv1108.c:125:7: warning: unused variable
'mux_pll_src_3plls_p' [-Wunused-const-variable]
PNAME(mux_pll_src_3plls_p)      = { "apll", "gpll", "dpll" };

Looks like this variable was never used. Deleting it to remove the
warning.

Cc: clang-built-linux@googlegroups.com
Link: https://github.com/ClangBuiltLinux/linux/issues/524
Signed-off-by: Nathan Huckleberry 
Reviewed-by: Nick Desaulniers 
Signed-off-by: Heiko Stuebner