linux.git/drivers/clk/rockchip, branch v4.20

clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call

2018-10-17T13:12:51+00:00

Fixes the signedness bug returning '(-22)' on the return type by removing the
sanity checker in rockchip_ddrclk_get_parent(). The function should return
and unsigned value only and it's safe to remove the sanity checker as the
core functions that call get_parent like clk_core_get_parent_by_index already
ensures the validity of the clk index returned (index >= core->num_parents).

Fixes: a4f182bf81f18 ("clk: rockchip: add new clock-type for the ddrclk")
Cc: stable@vger.kernel.org
Signed-off-by: Enric Balletbo i Serra 
Reviewed-by: Stephen Boyd 
Signed-off-by: Heiko Stuebner

clk: rockchip: use the newly added clock-id for hdmi on RK3066

2018-10-11T12:57:28+00:00

Export the clock for devicetree usage via the newly added id.

Signed-off-by: Heiko Stuebner

clk: rockchip: fix wrong mmc sample phase shift for rk3328

2018-10-11T12:36:01+00:00

mmc sample shift is 0 for RK3328 referring to the TRM.
So fix them.

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Cc: stable@vger.kernel.org
Signed-off-by: Ziyuan Xu 
Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: improve rk3288 pll rates for better hdmi output

2018-08-31T07:43:35+00:00

Add and correct PLL rates for better hdmi output.

This includes minimizing jitter on 213 MHz for better 71 MHz,
250.5 MHz for better 83.5 MHz, 428 MHz for better 25.175 Mhz,
low jitter 273 MHz for better 68.25 mhz, 356 MHz for better 118.68 Mhz
and 300MHz.

Increase the used Fvco for 308, 324 MHz, 292.5 MHz, 273.6 MHz,
238 MHz and 216 MHz.

And add some additional rates allowing to reach better hdmi-related
rates in general.

These match the rates used by ChromeOS, so have been quite widely tested.

Signed-off-by: Urja Rannikko 
Signed-off-by: Heiko Stuebner

clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399

2018-08-06T21:46:52+00:00

PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in
RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave
from power on and the VDD_LOG is about 0.9V. When the kernel boots
normally into the system, the PWM2 keeps outputing PWM signal.

But the kernel hangs randomly after "Starting kernel ..." line on that
board. When it happens, PWM2 outputs high level which causes VDD_LOG
drops to 0.4V below the normal operating voltage.

By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array,
PWM clock is ensured to be prepared at startup and the PWM2 output is
normal. After repeated tests, the early boot hang is gone.

This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards.

Signed-off-by: Levin Du 
Signed-off-by: Heiko Stuebner

clk: rockchip: fix clk_i2sout parent selection bits on rk3399

2018-07-07T22:19:19+00:00

Register, shift and mask were wrong according to datasheet.

Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Cc: stable@vger.kernel.org
Signed-off-by: Alberto Panizzo 
Signed-off-by: Anthony Brandon 
Signed-off-by: Heiko Stuebner

clk: rockchip: add clock controller for px30

2018-07-06T17:17:57+00:00

Add the clock tree definition for the new px30 SoC.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: add support for half divider

2018-07-06T17:17:57+00:00

The new Rockchip socs have optional half divider:
The formula is shown as:
	freq_out = 2*freq_in / (2*div + 3)
Is this the same for all of new SoCs.

So we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \
DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV"
to hook that special divider clock-type into our clock-tree.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: remove deprecated gate-clk code and dt-binding

2018-05-23T11:19:06+00:00

Initially we tried modeling clocks via the devicetree before switching
to clocks declared in the clock drivers and only exporting specific
ids to the devicetree.

As the old code was in the kernel for 1-2 releases when the new mode
of operation was added we kept it for backwards compatibility.

That deprecation notice is in the binding since july 2014, so nearly
4 years now and I think it's time to drop the old cruft.

Especially as at the time using the mainline kernel on Rockchip devices
was not really possible, except for experiments on the really old socs of
the rk3066 + rk3188 line, so there shouldn't be any devicetrees still
around that rely on that code.

Signed-off-by: Heiko Stuebner 
Acked-by: Stephen Boyd 
Reviewed-by: Rob Herring

clk: rockchip: use match_string() helper

2018-05-22T11:32:09+00:00

match_string() returns the index of an array for a matching string,
which can be used intead of open coded variant.

Cc: Michael Turquette 
Cc: Stephen Boyd 
Cc: Heiko Stuebner 
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Yisheng Xie 
Signed-off-by: Heiko Stuebner