linux.git/drivers/clk/rockchip, branch v4.19

clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399

2018-08-06T21:46:52+00:00

PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in
RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave
from power on and the VDD_LOG is about 0.9V. When the kernel boots
normally into the system, the PWM2 keeps outputing PWM signal.

But the kernel hangs randomly after "Starting kernel ..." line on that
board. When it happens, PWM2 outputs high level which causes VDD_LOG
drops to 0.4V below the normal operating voltage.

By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array,
PWM clock is ensured to be prepared at startup and the PWM2 output is
normal. After repeated tests, the early boot hang is gone.

This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards.

Signed-off-by: Levin Du 
Signed-off-by: Heiko Stuebner

clk: rockchip: fix clk_i2sout parent selection bits on rk3399

2018-07-07T22:19:19+00:00

Register, shift and mask were wrong according to datasheet.

Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Cc: stable@vger.kernel.org
Signed-off-by: Alberto Panizzo 
Signed-off-by: Anthony Brandon 
Signed-off-by: Heiko Stuebner

clk: rockchip: add clock controller for px30

2018-07-06T17:17:57+00:00

Add the clock tree definition for the new px30 SoC.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: add support for half divider

2018-07-06T17:17:57+00:00

The new Rockchip socs have optional half divider:
The formula is shown as:
	freq_out = 2*freq_in / (2*div + 3)
Is this the same for all of new SoCs.

So we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \
DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV"
to hook that special divider clock-type into our clock-tree.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: remove deprecated gate-clk code and dt-binding

2018-05-23T11:19:06+00:00

Initially we tried modeling clocks via the devicetree before switching
to clocks declared in the clock drivers and only exporting specific
ids to the devicetree.

As the old code was in the kernel for 1-2 releases when the new mode
of operation was added we kept it for backwards compatibility.

That deprecation notice is in the binding since july 2014, so nearly
4 years now and I think it's time to drop the old cruft.

Especially as at the time using the mainline kernel on Rockchip devices
was not really possible, except for experiments on the really old socs of
the rk3066 + rk3188 line, so there shouldn't be any devicetrees still
around that rely on that code.

Signed-off-by: Heiko Stuebner 
Acked-by: Stephen Boyd 
Reviewed-by: Rob Herring

clk: rockchip: use match_string() helper

2018-05-22T11:32:09+00:00

match_string() returns the index of an array for a matching string,
which can be used intead of open coded variant.

Cc: Michael Turquette 
Cc: Stephen Boyd 
Cc: Heiko Stuebner 
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Yisheng Xie 
Signed-off-by: Heiko Stuebner

clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399

2018-03-23T08:09:19+00:00

Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
and these two PLL may change their frequency. If we do not
assign right id to pclk_ddr and hclk_sd, they will alway use
default cur register value, and may get the frequency
exceed their signed off frequency. So assign correct Id
for them, then we can assign frequency for them in dts.

Signed-off-by: Lin Huang 
Reviewed-by: Douglas Anderson 
Reviewed-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: Fix error return in phase clock registration

2018-03-23T08:08:43+00:00

The newly added clock notifier may return an error code but so far the
error output in the function would only return an error pointer from
registering the clock.

So when the clock notifier fails the clock would be unregistered but the
return would still be the clock pointer which could then not be
dereferenced correctly. So fix the error handling to prevent that.

Fixes: 60cf09e45fbc ("clk: rockchip: Restore the clock phase after the rate was changed")
Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: Correct the behaviour of restoring cached phase

2018-03-23T08:02:58+00:00

We can't restore every phase, for instance the invalid phase and
the phase for coming rate which is out of the scope of boards'
ability. And this patch also corrects the error path to return
invalid pointer to clk if clk_notifier_register failed introduced
by the same offending commit.

Fixes: 60cf09e45fbc ("clk: rockchip: Restore the clock phase after the rate was changed")
Reported-by: wlq 
Signed-off-by: Shawn Lin 
Tested-by: wlq 
Signed-off-by: Heiko Stuebner

clk: rockchip: Fix wrong parents for MMC phase clock for rk3328

2018-03-23T07:58:19+00:00

commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if
clock rate is zero") catches some gremlins for clk-rk3328.c that the
parents of MMC phase clock should be clk_{sdmmc, sdio, emmc}, but not
sclk_{sdmmc, sdio, emmc}.

Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner