linux.git/drivers/clk/rockchip, branch v4.17

clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399

2018-03-23T08:09:19+00:00

Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
and these two PLL may change their frequency. If we do not
assign right id to pclk_ddr and hclk_sd, they will alway use
default cur register value, and may get the frequency
exceed their signed off frequency. So assign correct Id
for them, then we can assign frequency for them in dts.

Signed-off-by: Lin Huang 
Reviewed-by: Douglas Anderson 
Reviewed-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: Fix error return in phase clock registration

2018-03-23T08:08:43+00:00

The newly added clock notifier may return an error code but so far the
error output in the function would only return an error pointer from
registering the clock.

So when the clock notifier fails the clock would be unregistered but the
return would still be the clock pointer which could then not be
dereferenced correctly. So fix the error handling to prevent that.

Fixes: 60cf09e45fbc ("clk: rockchip: Restore the clock phase after the rate was changed")
Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: Correct the behaviour of restoring cached phase

2018-03-23T08:02:58+00:00

We can't restore every phase, for instance the invalid phase and
the phase for coming rate which is out of the scope of boards'
ability. And this patch also corrects the error path to return
invalid pointer to clk if clk_notifier_register failed introduced
by the same offending commit.

Fixes: 60cf09e45fbc ("clk: rockchip: Restore the clock phase after the rate was changed")
Reported-by: wlq 
Signed-off-by: Shawn Lin 
Tested-by: wlq 
Signed-off-by: Heiko Stuebner

clk: rockchip: Fix wrong parents for MMC phase clock for rk3328

2018-03-23T07:58:19+00:00

commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if
clock rate is zero") catches some gremlins for clk-rk3328.c that the
parents of MMC phase clock should be clk_{sdmmc, sdio, emmc}, but not
sclk_{sdmmc, sdio, emmc}.

Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228

2018-03-23T07:49:35+00:00

commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase
if clock rate is zero") catches one gremlin again for clk-rk3228.c
that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
sclk_sdmmc. However, the naming of the sdmmc clocks varies in the
manual with the card clock having the 0 while the hclk is named
without appended 0. So standardize one one format to prevent
confusion, as there also is only one (non-sdio) mmc controller on
the soc.

Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: Add 1.6GHz PLL rate for rk3399

2018-03-13T23:37:22+00:00

We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.

Signed-off-by: Derek Basehore 
Reviewed-by: Douglas Anderson 
Signed-off-by: Heiko Stuebner

clk: rockchip: Restore the clock phase after the rate was changed

2018-03-13T12:06:15+00:00

There are many factors affecting the clock phase, including clock
rate, temperature, logic voltage and silicon process, etc. But clock
rate is the most significant one here, and the driver should be aware
of the change of the clock rate. As mmc controller need a fixed phase
after tuning was completed, at least before explicitly doing re-tune,
so this patch try to restore the clock phase by monitoring the event
of rate change.

Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: Prevent calculating mmc phase if clock rate is zero

2018-03-05T20:37:13+00:00

The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.

Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: Free the memory on the error path

2018-03-02T07:51:03+00:00

rockchip_clk_register_branch() and rockchip_clk_register_frac_branch()
should free the memory internally when seeing any failure.

Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner

clk: rockchip: add flags for rk3328 dclk_lcdc

2018-02-12T14:00:55+00:00

dclk_lcdc can be sourced from a general pll source as well
as the hdmiphy's pll output. We will want to set this source
by hand (to the system-pll-source in most cases) and also
want rate changes to this clock to be able to also touch
the pll source clock if needed, so add CLK_SET_RATE_PARENT
and CLK_SET_RATE_NO_REPARENT for dclk_lcdc.

Signed-off-by: Zheng Yang 
[ammended commit message]
Signed-off-by: Heiko Stuebner