linux.git/drivers/clk/rockchip, branch v4.13

clk: rockchip: mark some special clk as critical on rk3368

2017-06-02T13:57:32+00:00

The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.

The ddrphy/ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: mark noc and some special clk as critical on rk3288

2017-06-02T13:54:20+00:00

The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.

The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: mark noc and some special clk as critical on rk3228

2017-06-02T13:51:11+00:00

The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them.
But this clks need enable,so make it as critical.

The ddrupctl/ddrmon/ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,

The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.

All these non-noc/non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch
and bus IDLE(or pd on/off).

The software is not very good to solve this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036

2017-06-02T13:42:38+00:00

No driver to handle this clk yet, but chip design requiress for this clock
supplying the ddr controller to be always on.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: add clock controller for rk3128

2017-06-02T12:49:35+00:00

Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: export more rk3228 clocks ids

2017-06-02T12:48:40+00:00

This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: add ids for rk3399 testclks used for camera handling

2017-06-02T12:48:38+00:00

clk_testout1 and clk_testout2 are used for camera handling, so add their ids.

Signed-off-by: Eddie Cai 
Signed-off-by: Heiko Stuebner

clk: rockchip: fix up the RK3228 clk cpu setting table

2017-05-17T17:50:37+00:00

support more cpu freq, and add armcore div setting.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

2017-04-12T16:50:34+00:00

Pull rockchip clk driver updates from Heiko Stuebner:

  General rockchip clock changes for 4.12. Contains some new clock-ids
  as well as fixups of the clock-ids on rk3368 timers, which were unused
  and completely wrong (more and differently named timers).
  Also there is one new clock on rk3328 using the muxgrf type, a fix for
  pll enablement which should wait for the pll to lock before continuing,
  some more critical clocks and the rename of the rk1108 to rv1108, as the
  soc seems to have been using a preliminary name before its actual release.
  The plan is to have the driver changes (pinctrl, clk) go through the
  respective maintainer trees and once everything landed in mainline do
  the rename of the devicetree files. With the dts-include change in the
  clock rename, we also keep everything compiling and thus bisectability.

* tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add pll_wait_lock for pll_enable
  clk: rockchip: rename RK1108 to RV1108
  dt-bindings: rk1108-cru: rename RK1108 to RV1108
  clk: rockchip: mark some rk3368 core-clks as critical
  clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
  clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
  clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
  clk: rockchip: fix up rk3368 timer-ids
  clk: rockchip: add rk3328 clk_mac2io_ext ID
  clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399

clk: rockchip: add pll_wait_lock for pll_enable

2017-03-22T17:33:22+00:00

If pll is power down,when power up pll need wait pll lock.
The reference documents section:
	PLL frequency change and lock check

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner