linux.git/drivers/clk/rockchip, branch v4.11

clk: rockchip: Make uartpll a child of the gpll on rk3036

2017-03-07T13:54:50+00:00

The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.

This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.

Signed-off-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd

clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036

2017-03-07T13:54:49+00:00

The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.

Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd

clk: rockchip: rk3288: make all niu clocks critical

2017-01-22T23:58:45+00:00

NIU clocks are related to the interconnect and it's important to other blocks.
Since we don't have a driver to handle it, we should always enable it to avoid
casually close.

Make all of them critical,so that we don't have to each clock on its own
once things break.

Signed-off-by: Jacob Chen 
[dropped the matching CLK_IGNORE_UNUSED flags]
Signed-off-by: Heiko Stuebner

clk: rockchip: use rk3288 vip_out clock ids

2017-01-22T16:08:01+00:00

Reference the newly added vip clock-ids in the clock-tree.

Signed-off-by: Jacob Chen 
Signed-off-by: Heiko Stuebner

clk: rockchip: fix the incorrect pclk_edp div width for RK3399

2017-01-18T10:23:36+00:00

The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang 
Signed-off-by: Xing Zheng 
Tested-by: Lin Huang 
Signed-off-by: Heiko Stuebner

clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188

2017-01-13T16:32:55+00:00

Add the newly added clock ids to the clock entries of the rk3066/rk3188
clock driver. We won't be needing them in the kernel for a bit yet
but as they're used in the new u-boot ddr setup code/dts we should make
sure the clock ids stay identical and do not differ.

Signed-off-by: Heiko Stuebner

clk: rockchip: use rk3288 isp_in clock ids

2017-01-13T16:13:48+00:00

Reference the newly added isp clock-ids in the clock-tree.

Signed-off-by: Jacob Chen 
Signed-off-by: Heiko Stuebner

clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER

2017-01-06T17:08:16+00:00

When we used to defer setting the "grf" member to
rockchip_clk_get_grf() it was important to init the "grf" member to an
error value in rockchip_clk_init().  With recent changes, we now set
"grf" right in rockchip_clk_init() (two lines below the place where we
initted it).  That makes the old init useless.  Get rid of it.

Fixes: 6f339dc2719e ("clk: rockchip: lookup General Register Files in rockchip_clk_init")
Signed-off-by: Douglas Anderson 
Signed-off-by: Heiko Stuebner

clk: rockchip: add clock controller for rk3328

2017-01-05T12:36:07+00:00

Add the clock tree definition for the new rk3328 SoC.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner

clk: rockchip: add new pll-type for rk3328

2017-01-02T13:24:57+00:00

The rk3328's pll and clock are similar with rk3036's,
it different with pll_mode_mask, the rk3328 soc
pll mode only one bit(rk3036 soc have two bits)
so these should be independent and separate from
the series of rk3328s.

Signed-off-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner