linux.git/drivers/clk/rockchip, branch v3.19

clk: rockchip: fix deadlock possibility in cpuclk

2015-01-17T19:22:39+00:00

Lockdep reported a possible deadlock between the cpuclk lock and for example
the i2c driver.

       CPU0                    CPU1
       ----                    ----
  lock(clk_lock);
                               local_irq_disable();
                               lock(&(&i2c->lock)->rlock);
                               lock(clk_lock);
  
    lock(&(&i2c->lock)->rlock);

 *** DEADLOCK ***

The generic clock-types of the core ccf already use spin_lock_irqsave when
touching clock registers, so do the same for the cpuclk.

Signed-off-by: Heiko Stuebner 
Reviewed-by: Doug Anderson 
Signed-off-by: Michael Turquette 
[mturquette@linaro.org: removed initialization of "flags"]

clk: rockchip: fix rk3288 cpuclk core dividers

2014-12-28T22:31:44+00:00

Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.

Reported-by: Sonny Rao 
Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: Heiko Stuebner 
Reviewed-by: Doug Anderson 
Cc: stable@vger.kernel.org

clk: rockchip: fix rk3066 pll lock bit location

2014-12-28T22:30:08+00:00

The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.

Signed-off-by: Heiko Stuebner 
Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: FUKAUMI Naoki 
Cc: stable@vger.kernel.org

clk: rockchip: Fix clock gate for rk3188 hclk_emem_peri

2014-12-21T14:21:28+00:00

Do not disable clock gate "hclk_emem_peri", otherwise EMAC clocks no longer work
and it breaks ethernet on RK3066 and RK3188. It fixes a regression introduced by
commit 78eaf6095cc7 ("clk: rockchip: disable unused clocks").

Signed-off-by: Romain Perier 
Fixes: 78eaf6095cc7 ("clk: rockchip: disable unused clocks")
Signed-off-by: Heiko Stuebner

clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB Host

2014-12-21T14:18:24+00:00

This patch adds CLK_IGNORE_UNUSED flag to hclk_usb_peri, hclk_usbotg0
and hclk_usbotg1 because these clocks must remain enabled to use the
USB controllers in host mode.

This fixes a regression introduced by commit 78eaf6095cc7
("clk: rockchip: disable unused clocks").

Signed-off-by: Julien CHAUVEAU 
Fixes: 78eaf6095cc7 ("clk: rockchip: disable unused clocks")
Reviewed-by: Romain Perier 
Tested-by: Romain Perier 
Signed-off-by: Heiko Stuebner

Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

2014-11-29T05:00:16+00:00

- clock phase setting capability for the rk3288 mmc clocks
- pll init to allow syncing to actual rate table values
- some more exported clocks
- fixes for some clocks (typos etc) all of them not yet used
  in actual drivers

clk: rockchip: Add support for the mmc clock phases using the framework

2014-11-27T23:44:24+00:00

This patch adds the 2 physical clocks for the mmc (drive and sample). They're
mostly there for the phase properties, but they also show the true clock
(by dividing by RK3288_MMC_CLKGEN_DIV).

The drive and sample phases are generated by dividing an upstream parent clock
by 2, this allows us to adjust the phase by 90 deg.

There's also an option to have up to 255 delay elements (40-80 picoseconds long).
This driver uses those elements (under the assumption that they're 60 ps long)
to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as
90 deg if the delay elements are as big as 80 ps, so a finer division (smaller
than 22.5) was not picked because the phase might not be monotonic anymore.

Suggested-by: Heiko Stuebner 
Signed-off-by: Alexandru M Stan 
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3288 export i2s0_clkout for use in DT

2014-11-27T23:37:47+00:00

This exposes the clock that comes out of the i2s block which generally
goes to the audio codec.

Signed-off-by: Sonny Rao 
[removed CLK_SET_RATE_PARENT from original patch]
Signed-off-by: Heiko Stuebner

clk: rockchip: use clock ID for DMC (memory controller) on rk3288

2014-11-26T17:32:28+00:00

The DMC clocks need to be turned off at runtime.  Use the newly
assigned clock IDs to export them.

Signed-off-by: Jeff Chen 
[dianders: split into two patches; adjusted commit msg]
Signed-off-by: Doug Anderson 
Signed-off-by: Heiko Stuebner

clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls

2014-11-25T08:57:22+00:00

Add the new flag to gpll and cpll on rk3188 and similar and to
gpll, cpll and npll on rk3288.

Signed-off-by: Heiko Stuebner 
Reviewed-by: Kever Yang 
Tested-by: Kever Yang