linux.git/drivers/clk/qcom, branch v7.2

Merge tag 'qcom-clk-fixes-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes

2026-08-10T18:35:50+00:00

Pull Qualcomm clock driver fixes from Bjorn Andersson:

 - Fix the Eliza display clock controller to avoid RCG stall.
   Revert the rework of the "PHY mux" clock, as this broke PCIe
   on several different targets
 - Drop (and correct one) bouncing maintainer email addresses in
   Qualcomm clk DeviceTree bindings

* tag 'qcom-clk-fixes-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  dt-bindings: clock: Replace bouncing emails
  Revert "clk: qcom: regmap-phy-mux: Rework the implementation"
  clk: qcom: dispcc-eliza: Fix disp_cc_mdss_mdp_clk_src RCG stall on Eliza EVK

Revert "clk: qcom: regmap-phy-mux: Rework the implementation"

2026-07-07T03:27:14+00:00

This reverts commit e108373c54fbc844b7f541c6fd7ecb31772afd3c.

This has been reported to break PCIe on at least SM8350 and Eliza
platforms. I had originally tested this on Hamoa (X1E) where there were
no adverse effects. It's highly likely that this stems from a
difference in how the bootloader configures the clocks.

Revert the offending change to fix the issue in the immediate, with the
intent to revisit it in the upcoming cycle.

Reported-by: Dmitry Baryshkov 
Reported-by: Abel Vesa 
Signed-off-by: Konrad Dybcio 
Fixes: e108373c54fb ("clk: qcom: regmap-phy-mux: Rework the implementation")
Closes: https://lore.kernel.org/all/c675lcfptr4xgg4hcjp66unmuozgsvgwvtymh7on6jcipjrdw7@jy4h7fkwqwjg/
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20260622-topic-phymux_revert-v1-1-f6ec85523840@oss.qualcomm.com
Signed-off-by: Bjorn Andersson

Replace by more specific (c files)

2026-07-03T05:38:17+00:00

Replace the #include of  by the more specific
 where applicable. For most cases the include
can be dropped completely, only a few drivers need one or two headers
added.

Acked-by: Danilo Krummrich 
Acked-by: Takashi Sakamoto 
Acked-by: Bjorn Helgaas 
Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König (The Capable Hub)

clk: qcom: dispcc-eliza: Fix disp_cc_mdss_mdp_clk_src RCG stall on Eliza EVK

2026-06-29T02:51:05+00:00

Eliza EVK (eliza-cqs-evk.dts) does not have display enabled, however its
Display Clock Controller is enabled and references parent clocks from
DSI PHYs, which causes clock reparenting issues during probe (init) and
warning on Eliza EVK:

  disp_cc_mdss_mdp_clk_src: rcg didn't update its configuration.
  WARNING: drivers/clk/qcom/clk-rcg2.c:136 at update_config+0xd4/0xe4, CPU#1: udevd/273
  ...
    update_config (drivers/clk/qcom/clk-rcg2.c:136 (discriminator 2)) (P)
    clk_rcg2_shared_disable (drivers/clk/qcom/clk-rcg2.c:1471)
    clk_rcg2_shared_init (drivers/clk/qcom/clk-rcg2.c:1540)
    __clk_register (drivers/clk/clk.c:3959 drivers/clk/clk.c:4368)
    devm_clk_hw_register (drivers/clk/clk.c:4448 (discriminator 1) drivers/clk/clk.c:4672 (discriminator 1))
    devm_clk_register_regmap (drivers/clk/qcom/clk-regmap.c:104)
    qcom_cc_really_probe (drivers/clk/qcom/common.c:418)
    qcom_cc_probe (drivers/clk/qcom/common.c:445)
    disp_cc_eliza_probe (dispcc-eliza.c:?) dispcc_eliza
    platform_probe (drivers/base/platform.c:1432)

Fixes: 0e66f10942b5 ("clk: qcom: dispcc-eliza: Add Eliza display clock controller support")
Signed-off-by: Krzysztof Kozlowski 
Reviewed-by: Konrad Dybcio 
Reviewed-by: Taniya Das 
Link: https://lore.kernel.org/r/20260623115644.392477-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2026-06-25T19:48:57+00:00

Pull clk updates from Stephen Boyd:
 "This is all clk driver updates. Mostly new SoC support for various
  Qualcomm chips and Canaan K230. Otherwise there's non-critical fixes
  and updates to clk data such as adding missing clks to existing
  drivers or marking clks critical. Nothing looks especially exciting"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (106 commits)
  clk: qcom: regmap-phy-mux: Rework the implementation
  clk: qcom: a53: Corrected frequency multiplier for 1152MHz
  clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC
  clk: qcom: gdsc: Support enabling interconnect path for power domain
  dt-bindings: clock: qcom,milos-camcc: Document interconnect path
  interconnect: Add devm_of_icc_get_by_index() as exported API for users
  clk: qcom: camcc-x1p42100: Add support for camera clock controller
  clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks
  clk: qcom: videocc-x1p42100: Add support for video clock controller
  dt-bindings: clock: qcom: Add X1P42100 camera clock controller
  dt-bindings: clock: qcom: Add X1P42100 video clock controller
  clk: keystone: sci-clk: fix application of sizeof to pointer
  clk: keystone: don't cache clock rate
  clk: spacemit: k3: Add PCIe DBI clock
  dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
  clk: spacemit: k3: Fix PCIe clock register offset
  clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
  clk: at91: keep securam node alive while mapping it
  clk: samsung: exynos990: Fix PERIC0/1 USI clock types
  clk: renesas: r9a08g045: Drop unused pm_domain header file
  ...

clk: qcom: regmap-phy-mux: Rework the implementation

2026-06-08T14:17:24+00:00

The sole reason this hw exists is to let the branch clock downstream of
it keep running, with the PHY disengaged. This is not possible with the
current implementation, as the enabled status is hijacked to mean
"enabled" = "use fast/PHY source" and "disabled" = "use XO source".

This is an issue, since the mux enable state follows that of the child
branch, making the desired "child enabled, MUX @ XO" combination
impossible.

Solve that by implementing ratesetting. Because PHY clock rates may
change at runtime and aren't really deterministic from Linux, assume
ULONG_MAX as "fast clock" and 19.2 MHz as XO. All the branches in
question already set CLK_SET_RATE_PARENT, so everything works out.

Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20260409-topic-phy_fastclk-v1-1-6b4aaee56b90@oss.qualcomm.com
Signed-off-by: Bjorn Andersson

clk: qcom: a53: Corrected frequency multiplier for 1152MHz

2026-06-08T14:08:55+00:00

The 1152MHz frequency entry for the a53 currently selects a multiplier of 62, giving 1190MHz. This changes the mulitiplier to 60 giving the intended 1152MHz.

Signed-off-by: Phillip Varney 
Reviewed-by: Konrad Dybcio 
Fixes: 0c6ab1b8f894 ("clk: qcom: Add A53 PLL support")
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20260605005502.313928-1-pbvarney@protonmail.com
Signed-off-by: Bjorn Andersson

clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC

2026-06-07T00:51:15+00:00

This GDSC requires an interconnect path to be enabled, otherwise the
GDSC will be stuck on 'off' and can't be enabled.

Reviewed-by: Konrad Dybcio 
Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Luca Weiss 
Link: https://lore.kernel.org/r/20260501-milos-camcc-icc-v2-4-bb83c1256cc3@fairphone.com
Signed-off-by: Bjorn Andersson

clk: qcom: gdsc: Support enabling interconnect path for power domain

2026-06-07T00:51:15+00:00

On newer SoCs like Milos the CAMSS_TOP_GDSC power domains requires the
enablement of the multimedia NoC, otherwise the GDSC will be stuck on
'off'.

Add support for getting an interconnect path as specified in the SoC
clock driver, and enabling/disabling that interconnect path when the
GDSC is being enabled/disabled.

Signed-off-by: Luca Weiss 
Link: https://lore.kernel.org/r/20260501-milos-camcc-icc-v2-3-bb83c1256cc3@fairphone.com
Signed-off-by: Bjorn Andersson

clk: qcom: camcc-x1p42100: Add support for camera clock controller

2026-06-07T00:50:16+00:00

Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on X1P42100 platform. Although
X1P42100 is derived from X1E80100, the camera clock controller driver
differs significantly. Few PLLs, clocks and GDSC's are removed, there
is delta in frequency tables for most RCG's and parent data structures
also changed for few RCG's. Hence introduce a separate camcc driver
for X1P42100 platform.

Reviewed-by: Konrad Dybcio 
Reviewed-by: Taniya Das 
Signed-off-by: Jagadeesh Kona 
Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-5-fc3af4130282@oss.qualcomm.com
Signed-off-by: Bjorn Andersson