linux.git/drivers/clk/qcom/common.c, branch v4.5

clk: qcom: common: Add API to register board clocks backwards compatibly

2015-11-16T19:07:06+00:00

We want to put the XO board clocks into the dt files, but we also
need to be backwards compatible with an older dtb. Add an API to
the common code to do this. This also makes a place for us to
handle the case when the RPM clock driver is enabled and we don't
want to register the fixed factor clock.

Cc: Georgi Djakov 
Signed-off-by: Stephen Boyd

clk: qcom: Drop calls to qcom_cc_remove()

2015-10-09T06:53:01+00:00

Now that qcom_cc_remove() is a nop, drop calls to
qcom_cc_remove() and any empty driver remove functions.

Cc: Rajendra Nayak 
Signed-off-by: Stephen Boyd

qcom: clk: Make qcom_cc_probe() fully devm safe

2015-10-09T06:53:00+00:00

Some APIs in qcom_cc_probe() don't have a devm counterpart, so we
have to use the calling device's platform data to pass pointers
to the remove path. Let's use devm_add_action() instead, so that
the remove path doesn't need to do anything, allowing us to
remove qcom_cc_remove() entirely.

Cc: Rajendra Nayak 
Signed-off-by: Stephen Boyd

clk: qcom: gdsc: Add support for ON only state

2015-09-16T22:22:40+00:00

Certain devices can have GDSCs' which support ON as the only state.
They can't be power collapsed to either hit RET or OFF.
The clients drivers for these GDSCs' however would expect the state
of the core to be reset following a GDSC disable and re-enable.
To do this assert/deassert reset lines every time the client
driver would request the GDSC to be powered on/off instead.

Signed-off-by: Rajendra Nayak 
Signed-off-by: Stephen Boyd

clk: qcom: gdsc: Prepare common clk probe to register gdscs

2015-09-16T22:22:37+00:00

The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.

Signed-off-by: Rajendra Nayak 
Signed-off-by: Stephen Boyd

clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()

2015-08-24T23:48:43+00:00

Mostly converted with the following semantic patch:

@@
struct clk_hw *E;
@@

-__clk_get_num_parents(E->clk)
+clk_hw_get_num_parents(E)

Acked-by: Boris Brezillon 
Cc: Chao Xie 
Cc: Krzysztof Kozlowski 
Cc: Javier Martinez Canillas 
Cc: Tomasz Figa 
Cc: Maxime Ripard 
Cc: "Emilio López" 
Acked-by: Tero Kristo 
Cc: Geert Uytterhoeven 
Acked-by: Sylwester Nawrocki 
Signed-off-by: Stephen Boyd

clk: qcom: Give clk-qcom.ko module a GPLv2 license

2015-07-28T18:59:26+00:00

The missing license causes the clk-qcom.ko module to taint the
kernel. Add the appropriate license to avoid taint.

Signed-off-by: Stephen Boyd

clk: qcom: Introduce parent_map tables

2015-03-23T23:09:19+00:00

In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.

This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
 - Define a parent_map struct to map the relations between PLL source index
 and register configuration value.
 - Add a qcom_find_src_index() function for finding the index of a clock
 matching the specific PLL configuration.
 - Update the {set,get}_parent RCG functions use the newly introduced
 parent_map struct.
 - Convert all existing drivers to the new parent_map tables.

Signed-off-by: Georgi Djakov 
Signed-off-by: Stephen Boyd

clk: qcom: Consolidate frequency finding logic

2014-09-22T22:16:52+00:00

There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.

Cc: Mike Turquette 
Signed-off-by: Stephen Boyd

clk: qcom: Fix PLL rate configurations

2014-07-15T23:39:00+00:00

Sometimes we need to program PLLs with a fixed rate
configuration during driver probe. Doing this after we register
the PLLs with the clock framework causes the common clock
framework to assume the rate of the PLLs are 0. This causes all
sorts of problems for rate recalculations because the common
clock framework caches the rate once at registration time unless
a flag is set to always recalculate the rates.

Split the qcom_cc_probe() function into two pieces, map and
everything else, so that drivers which need to configure some
PLL rates or otherwise twiddle bits in the clock controller can
do so before registering clocks. This allows us to properly
detect the rates of PLLs that are programmed at boot.

Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code"
Signed-off-by: Stephen Boyd