linux.git/drivers/clk/qcom/Makefile, branch v6.0

clk: qcom: add support for SM8350 GPUCC

2022-07-06T20:20:59+00:00

The GPUCC manages the clocks for the Adreno GPU found on the
sm8350 SoCs.

Signed-off-by: Robert Foss 
Signed-off-by: Jonathan Marek 
Reviewed-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220706154337.2026269-3-robert.foss@linaro.org

clk: qcom: add camera clock controller driver for SM8450 SoC

2022-07-06T20:20:59+00:00

Add  camera clock controller driver found on Qualcomm SM8450 SoC.

Reviewed-by: Bjorn Andersson 
Signed-off-by: Vladimir Zapolskiy 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220701062744.2757931-1-vladimir.zapolskiy@linaro.org

clk: qcom: regmap: add PHY clock source implementation

2022-06-26T02:36:07+00:00

On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.

Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. Supplement the regmap-mux with
the new clk_regmap_phy_mux type, which implements such multiplexers
as a simple gate clocks.

This is possible since each of these multiplexers has just two clock
sources: one coming from the PHY and a reference (XO) one.  If the clock
is running off the from-PHY source, report it as enabled. Report it as
disabled otherwise (if it uses reference source).

This way the PHY will disable the pipe clock before turning off the
GDSC, which in turn would lead to disabling corresponding pipe_clk_src
(and thus it being parked to a safe, reference clock source). And vice
versa, after enabling the GDSC the PHY will enable the pipe clock, which
would cause pipe_clk_src to be switched from a safe source to the
working one.

Reviewed-by: Johan Hovold 
Tested-by: Johan Hovold 
Reported-by: kernel test robot 
Signed-off-by: Dmitry Baryshkov 
Reviewed-by: Stephen Boyd 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220608105238.2973600-2-dmitry.baryshkov@linaro.org

clk: qcom: add sc8280xp GCC driver

2022-05-19T21:41:32+00:00

Add support for the Global Clock Controller found in the Qualcomm
SC8280XP platform.

Signed-off-by: Bjorn Andersson 
Reviewed-by: Vinod Koul 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org

clk: qcom: lpass: Add support for LPASS clock controller for SC7280

2022-04-13T02:17:42+00:00

The Low Power Audio subsystem core and audio clocks are required for
Audio client to be able to request for the clocks and power domains.

Signed-off-by: Taniya Das 
Reviewed-by: Stephen Boyd 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220223172248.18877-2-tdas@codeaurora.org

clk: qcom: Add display clock controller driver for SM6125

2022-03-09T14:53:30+00:00

Add support for the display clock controller found on SM6125
based devices. This allows display drivers to probe and
control their clocks.

Signed-off-by: Martin Botka 
Signed-off-by: Marijn Suijten 
Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220303131812.302302-4-marijn.suijten@somainline.org

clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig

2022-03-09T14:53:29+00:00

In order to keep at least the list of `CONFIG_SM_` drivers sorted
alphabetically, SDX_GCC_65 should have been moved one line up.  This in
turn makes it easier and cleaner to add the followup SM_DISPCC_6125
driver in the right place, right before SM_DISPCC_8250.

Fixes: d79afa201328 ("clk: qcom: Add SDX65 GCC support")
Signed-off-by: Marijn Suijten 
Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220303131812.302302-2-marijn.suijten@somainline.org

clk: qcom: Add GPU clock controller driver for SM6350

2022-03-08T22:16:47+00:00

Add support for the GPU clock controller found on SM6350.

Signed-off-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220222011534.3502-4-konrad.dybcio@somainline.org

clk: qcom: Add display clock controller driver for SM6350

2022-03-08T22:16:47+00:00

Add support for the display clock controller found on SM6350.

Signed-off-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220222011534.3502-2-konrad.dybcio@somainline.org

clk: qcom: Add display clock controller driver for QCM2290

2022-02-10T23:56:10+00:00

Add support for the display clock controller found in QCM2290
based devices. This clock controller feeds the Multimedia Display
SubSystem (MDSS).

It's a porting of dispcc-scuba GPL-2.0 driver from CAF msm-4.19 kernel:
https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/drivers/clk/qcom/dispcc-scuba.c?h=LE.UM.4.4.1.r3

Global clock name references (parent_names) have been replaced by
parent_data and parent_hws.

Clocks marked enable_safe_config have their clk_rcg2_ops moved to
clk_rcg2_shared_ops.

Signed-off-by: Loic Poulain 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/1644432308-21099-2-git-send-email-loic.poulain@linaro.org