linux.git/drivers/clk/nxp, branch v4.16

Merge branch 'clk-divider-container' into clk-next

2018-01-27T00:43:14+00:00

* clk-divider-container:
  clk: divider: fix incorrect usage of container_of

Plus fixup sprd/div.c to pass the width too.

clk: divider: fix incorrect usage of container_of

2017-12-28T23:16:04+00:00

divider_recalc_rate() is an helper function used by clock divider of
different types, so the structure containing the 'hw' pointer is not
always a 'struct clk_divider'

At the following line:
> div = _get_div(table, val, flags, divider->width);

in several cases, the value of 'divider->width' is garbage as the actual
structure behind this memory is not a 'struct clk_divider'

Fortunately, this width value is used by _get_val() only when
CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so
far when the structure is not a 'struct clk_divider'. This is probably
why we did not notice this bug before

Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero")
Signed-off-by: Jerome Brunet 
Acked-by: Alexandre Belloni 
Acked-by: Sylvain Lemieux 
Signed-off-by: Stephen Boyd

clk: lpc32xx: pr_err() strings should end with newlines

2017-12-07T06:39:53+00:00

pr_err() messages should end with a new-line to avoid other messages
being concatenated.

Signed-off-by: Arvind Yadav 
Acked-by: Vladimir Zapolskiy 
Signed-off-by: Stephen Boyd

clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()

2017-09-01T01:35:44+00:00

We need to export clk_gate_is_enabled() from clk framework, then
to avoid compilation issue we have to rename clk_gate_is_enabled()
in NXP LPC32xx clock driver.
We changed all gate op with 'lpc32xx_' prefix:
lpc32xx_clk_gate_enable(),
lpc32xx_clk_gate_disable(),
lpc32xx_clk_gate_is_enabled().

Signed-off-by: Gabriel Fernandez 
Acked-by: Vladimir Zapolskiy 
Signed-off-by: Stephen Boyd

clk: nxp: clk-lpc18xx-ccu: Unmap region obtained by of_iomap

2016-11-02T00:32:25+00:00

Free memory mapping, if lpc18xx_ccu_init() is not successful.

Signed-off-by: Arvind Yadav 
Acked-by: Joachim Eastwood 
Signed-off-by: Stephen Boyd

clk: lpc32xx: add a quirk for PWM and MS clock dividers

2016-11-02T00:29:39+00:00

In common clock framework CLK_DIVIDER_ONE_BASED or'ed with
CLK_DIVIDER_ALLOW_ZERO flags indicates that
1) a divider clock may be set to zero value,
2) divider's zero value is interpreted as a non-divided clock.

On the LPC32xx platform clock dividers of PWM and memory card clocks
comply with the first condition, but zero value means a gated clock,
thus it may happen that the divider value is not updated when
the clock is enabled and the clock remains gated.

The change adds one-shot quirks, which check for zero value of divider
on initialization and set it to a non-zero value, therefore in runtime
a gate clock will work as expected.

Signed-off-by: Vladimir Zapolskiy 
Reviewed-by: Sylvain Lemieux 
Signed-off-by: Stephen Boyd

clk: nxp: clk-lpc32xx: Unmap region obtained by of_iomap

2016-09-21T20:46:21+00:00

Free memory mapping, if lpc32xx_clk_init is not successful.

Signed-off-by: Arvind Yadav 
Acked-by: Vladimir Zapolskiy 
Acked-by: Sylvain Lemieux 
Signed-off-by: Stephen Boyd

clk: nxp: Use new macro CLK_OF_DECLARE_DRIVER

2016-08-13T01:00:48+00:00

This driver initializes a clock provider via lpc18xx_creg_clk_init
and then continues the initialization on lpc18xx_creg_clk_probe.

Use the new macro to notify the clk subsystem about this behaviour.

Signed-off-by: Ricardo Ribalda Delgado 
[sboyd@codeaurora.org: s/npx/nxp/ in subject]
Signed-off-by: Stephen Boyd

clk: lpc32xx: allow peripheral clock selection in device tree

2016-07-07T00:51:14+00:00

This patch add the support to select the peripheral clock (PERIPH)
as a parent clock source using the "assigned-clock-parents"
parameter in the device tree.

Signed-off-by: Sylvain Lemieux 
Acked-by: Vladimir Zapolskiy 
Signed-off-by: Michael Turquette 
Link: lkml.kernel.org/r/1464982475-24738-1-git-send-email-slemieux.tyco@gmail.com

clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0

2016-05-06T17:55:11+00:00

Failure to initialize this flag to 0 by default can result in
stack junk filling the clk_init_data structure and weird things
happen. Joachim noticed that the critical clk feature started
triggering for these clks causing boot failures, when it really
shouldn't have happened:

BUG: scheduling while atomic: swapper/0/0x00000002
CPU: 0 PID: 0 Comm: swapper Not tainted
4.6.0-rc6-next-20160505-00001-g5c8320450d1c #826
Hardware name: NXP LPC18xx/43xx (Device Tree)
[<2800be81>] (unwind_backtrace) from [<2800b22f>] (show_stack+0xb/0xc)
[<2800b22f>] (show_stack) from [<2801ea21>] (__schedule_bug+0x2d/0x44)
[<2801ea21>] (__schedule_bug) from [<281dc937>] (__schedule+0x3b/0x268)
[<281dc937>] (__schedule) from [<281dcbbb>] (schedule+0x57/0x64)
[<281dcbbb>] (schedule) from [<281de8ef>] (schedule_timeout+0xfb/0x120)
[<281de8ef>] (schedule_timeout) from [<28030fcd>] (msleep+0xf/0x12)
[<28030fcd>] (msleep) from [<28165a6d>] (clk_creg_32k_prepare+0x1f/0x24)
[<28165a6d>] (clk_creg_32k_prepare) from [<281620d5>]
(clk_core_prepare+0x1d/0x36)
[<281620d5>] (clk_core_prepare) from [<2816340b>] (clk_register+0x22f/0x318)
[<2816340b>] (clk_register) from [<282b06c9>] (lpc18xx_creg_clk_init+0x55/0x84)
[<282b06c9>] (lpc18xx_creg_clk_init) from [<282b0149>] (of_clk_init+0xc1/0x12c)
[<282b0149>] (of_clk_init) from [<282a665d>] (time_init+0x15/0x20)
[<282a665d>] (time_init) from [<282a457d>] (start_kernel+0x169/0x274)
[<282a457d>] (start_kernel) from [<28008025>] (0x28008025)
bad: scheduling from the idle thread!
CPU: 0 PID: 0 Comm: swapper Tainted: G W
4.6.0-rc6-next-20160505-00001-g5c8320450d1c #826

Fix this by initializing the flags member to 0.

Acked-by: Joachim Eastwood 
Signed-off-by: Stephen Boyd