linux.git/drivers/clk/mmp, branch v6.7

clk: pxa910: Move number of clocks to driver source

2023-08-22T21:14:17+00:00

The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović 
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-4-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley 
Signed-off-by: Stephen Boyd

clk: pxa1928: Move number of clocks to driver source

2023-08-22T21:14:14+00:00

The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović 
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-3-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley 
Signed-off-by: Stephen Boyd

clk: pxa168: Move number of clocks to driver source

2023-08-22T21:14:06+00:00

The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović 
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-2-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley 
Signed-off-by: Stephen Boyd

clk: mmp2: Move number of clocks to driver source

2023-08-22T21:13:45+00:00

The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović 
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-1-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley 
Signed-off-by: Stephen Boyd

clk: mmp: Remove old non-OF clock drivers

2023-08-22T21:13:11+00:00

There are no MMP2, PXA168 or PXA910 boards still using board files which
would use these drivers, so remove them.

Signed-off-by: Duje Mihanović 
Link: https://lore.kernel.org/r/20230804-drop-old-mmp-clk-v1-1-0c07db6cee90@skole.hr
Signed-off-by: Stephen Boyd

clk: mmp: Convert to platform remove callback returning void

2023-03-29T02:31:44+00:00

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König 
Link: https://lore.kernel.org/r/20230312161512.2715500-21-u.kleine-koenig@pengutronix.de
Signed-off-by: Stephen Boyd

clk: mmp: pxa168: control shared SDH bits with separate clock

2022-09-30T20:34:07+00:00

The PXA168 has a peculiar setup with the AXI clock enable control for
the SDHC controllers. The bits in the SDH0 register control the AXI
clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2
register control both SDH2 and SDH3. This is modeled with two new
parentless clocks that control the shared bits.

Previously, SDH0 had to be enabled in order for SDH1 to be used, and
when SDH1 was enabled, unused bits in the SDH1 register were being
controlled. This fixes those issues. A future commit will add support
for these new shared clocks to be enabled by the PXA168 SDHC driver.

Signed-off-by: Doug Brown 
Link: https://lore.kernel.org/r/20220612192937.162952-13-doug@schmorgal.com
Signed-off-by: Stephen Boyd

clk: mmp: pxa168: add clocks for SDH2 and SDH3

2022-09-30T20:34:07+00:00

The PXA168 has four SDHC peripherals. This commit adds the last two.

Signed-off-by: Doug Brown 
Link: https://lore.kernel.org/r/20220612192937.162952-11-doug@schmorgal.com
Signed-off-by: Stephen Boyd

clk: mmp: pxa168: fix GPIO clock enable bits

2022-09-30T20:34:06+00:00

According to the datasheet, only bit 0 of APBC_GPIO should be controlled
for the clock enable. Bit 1 is marked as reserved (always write 0).

Signed-off-by: Doug Brown 
Link: https://lore.kernel.org/r/20220612192937.162952-9-doug@schmorgal.com
Signed-off-by: Stephen Boyd

clk: mmp: pxa168: add muxes for more peripherals

2022-09-30T20:34:06+00:00

The TWSI, KPC, PWM, and DFC peripherals didn't have their muxes modeled
in the code, but the PXA168 datasheet shows that they are indeed muxed:

- TWSI can be 31.2 MHz or 62.4 MHz
- KPC can be 32 kHz, 16 kHz, or 26 MHz
- PWM can be 13 MHz or 32 kHz
- DFC can be 156 MHz or 78 MHz

Signed-off-by: Doug Brown 
Link: https://lore.kernel.org/r/20220612192937.162952-8-doug@schmorgal.com
Signed-off-by: Stephen Boyd