linux.git/drivers/clk/meson, branch v6.5

clk: meson: change usleep_range() to udelay() for atomic context

2023-07-11T09:35:42+00:00

The function meson_clk_pll_enable() can be invoked under the enable_lock
spinlock from the clk core logic, which risks a kernel panic during the
usleep_range() call:

   BUG: scheduling while atomic: kworker/u4:2/36/0x00000002
   Modules linked in: g_ffs usb_f_fs libcomposite
   CPU: 1 PID: 36 Comm: kworker/u4:2 Not tainted 6.4.0-rc5 #273
   Workqueue: events_unbound async_run_entry_fn
   Call trace:
    dump_backtrace+0x9c/0x128
    show_stack+0x20/0x38
    dump_stack_lvl+0x48/0x60
    dump_stack+0x18/0x28
    __schedule_bug+0x58/0x78
    __schedule+0x828/0xa88
    schedule+0x64/0xd8
    schedule_hrtimeout_range_clock+0xd0/0x208
    schedule_hrtimeout_range+0x1c/0x30
    usleep_range_state+0x6c/0xa8
    meson_clk_pll_enable+0x1f4/0x310
    clk_core_enable+0x78/0x200
    clk_core_enable+0x58/0x200
    clk_core_enable+0x58/0x200
    clk_core_enable+0x58/0x200
    clk_enable+0x34/0x60

So it is required to use the udelay() function instead of usleep_range()
for the atomic context safety.

Fixes: b6ec400aa153 ("clk: meson: introduce new pll power-on sequence for A1 SoC family")
Reported-by: Jan Dakinevich 
Signed-off-by: Dmitry Rokosov 
Link: https://lore.kernel.org/r/20230704215404.11533-1-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet

clk: meson: pll: remove unneeded semicolon

2023-06-15T10:29:10+00:00

No functional modification involved.

./drivers/clk/meson/clk-pll.c:373:2-3: Unneeded semicolon.

Reported-by: Abaci Robot 
Signed-off-by: Jiapeng Chong 
Reviewed-by: Martin Blumenstingl 
Link: https://lore.kernel.org/r/20230614084808.98819-1-jiapeng.chong@linux.alibaba.com
Fixes: b6ec400aa153 ("clk: meson: introduce new pll power-on sequence for A1 SoC family")
Signed-off-by: Jerome Brunet

clk: meson: a1: Staticize rtc clk

2023-06-12T21:29:24+00:00

Sparse rightly complains that this symbol is supposed to be static.

Cc: Jian Hu 
Cc: Dmitry Rokosov 
Cc: Martin Blumenstingl 
Cc: Jerome Brunet 
Fixes: 84af914404db ("clk: meson: a1: add Amlogic A1 Peripherals clock controller driver")
Link: https://lore.kernel.org/r/20230612182332.371003-1-sboyd@kernel.org
Reviewed-by: Jerome Brunet 
Reviewed-by: Martin Blumenstingl 
Signed-off-by: Stephen Boyd

clk: meson: a1: add Amlogic A1 Peripherals clock controller driver

2023-05-30T15:53:09+00:00

Introduce Peripherals clock controller for Amlogic A1 SoC family.

A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU,
and Audio.
This patchset adds support for Amlogic A1 Peripherals clock driver and
allows to generate clocks for all A1 SoC peripheral IPs.

Signed-off-by: Jian Hu 
Signed-off-by: Dmitry Rokosov 
Reviewed-by: Martin Blumenstingl 
Link: https://lore.kernel.org/r/20230523135351.19133-7-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet

clk: meson: a1: add Amlogic A1 PLL clock controller driver

2023-05-30T15:53:05+00:00

Introduce PLL clock controller for Amlogic A1 SoC family.
The clock unit is an APB slave module that is designed for generating all
of the internal and system clocks.
The SoC uses an external 24MHz crystal; there are 4 internal PLLs:
SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources.

Signed-off-by: Jian Hu 
Signed-off-by: Dmitry Rokosov 
Reviewed-by: Martin Blumenstingl 
Link: https://lore.kernel.org/r/20230523135351.19133-5-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet

clk: meson: introduce new pll power-on sequence for A1 SoC family

2023-05-30T15:53:00+00:00

Modern meson PLL IPs are a little bit different from early known PLLs.
The main difference is located in the init/enable/disable sequences; the
rate logic is the same.

In A1 PLL, the PLL enable sequence is different, so add new optional pll
reg bits and use the new power-on sequence to enable the PLL:
    1. enable the pll, delay for 10us
    2. enable the pll self-adaption current module, delay for 40us
    3. enable the lock detect module

Signed-off-by: Jian Hu 
Acked-by: Martin Blumenstingl 
Signed-off-by: Dmitry Rokosov 
Link: https://lore.kernel.org/r/20230523135351.19133-3-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet

clk: meson: make pll rst bit as optional

2023-05-30T15:52:52+00:00

Compared with the previous SoCs, self-adaption current module
is newly added for A1, and there is no reset parameter except the
fixed pll. Since we use clk-pll generic driver for A1 pll
implementation, rst bit should be optional to support new behavior.

Signed-off-by: Jian Hu 
Acked-by: Martin Blumenstingl 
Signed-off-by: Dmitry Rokosov 
Link: https://lore.kernel.org/r/20230523135351.19133-2-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet

clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate

2023-01-13T14:14:12+00:00

clk_ops.round_rate will be removed at some point. It's replacement is
.determine_rate. Switch clk-cpu-dyndiv over to use .determine_rate.

Signed-off-by: Martin Blumenstingl 
Acked-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20221225212632.2760126-5-martin.blumenstingl@googlemail.com
Signed-off-by: Jerome Brunet

clk: meson: sclk-div: switch from .round_rate to .determine_rate

2023-01-13T14:14:12+00:00

clk_ops.round_rate will be removed at some point. It's replacement is
.determine_rate. Switch sclk-div over to use .determine_rate.

Signed-off-by: Martin Blumenstingl 
Acked-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20221225212632.2760126-4-martin.blumenstingl@googlemail.com
Signed-off-by: Jerome Brunet

clk: meson: dualdiv: switch from .round_rate to .determine_rate

2023-01-13T14:14:12+00:00

clk_ops.round_rate will be removed at some point. It's replacement is
.determine_rate. Switch clk-dualdiv over to use .determine_rate.

Signed-off-by: Martin Blumenstingl 
Acked-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20221225212632.2760126-3-martin.blumenstingl@googlemail.com
Signed-off-by: Jerome Brunet