linux.git/drivers/clk/meson, branch v5.8

clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers

2020-05-01T23:53:32+00:00

Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers.
In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when
booting Linux the PLL fails to lock.
The initialization sequence from u-boot is:
- put the PLL into reset
- write 0x59C88000 to HHI_GP_PLL_CNTL2
- write 0xCA463823 to HHI_GP_PLL_CNTL3
- write 0x0286A027 to HHI_GP_PLL_CNTL4
- write 0x00003000 to HHI_GP_PLL_CNTL5
- set M, N, OD and the enable bit
- take the PLL out of reset
- check if it has locked
- disable the PLL

In Linux we already initialize M, N, OD, the enable and the reset bits.
Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the
exact meaning is unknown) so the PLL can lock when the vendor u-boot did
not initialize these registers yet.

Fixes: b882964b376f21 ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2")
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20200501215717.735393-1-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Make the CCF use the glitch-free VPU mux

2020-04-29T08:26:53+00:00

The "vpu_0" or "vpu_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"vpu_0" and "vpu_1" gates. This makes the CCF switch to the "vpu_1"
tree when "vpu_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the VPU
clock.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20200417184127.1319871-5-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits

2020-04-29T08:26:53+00:00

The DIV{1,2,4,6,12}_EN bits are actually located in HHI_VID_CLK_CNTL
register:
- HHI_VID_CLK_CNTL[0] = DIV1_EN
- HHI_VID_CLK_CNTL[1] = DIV2_EN
- HHI_VID_CLK_CNTL[2] = DIV4_EN
- HHI_VID_CLK_CNTL[3] = DIV6_EN
- HHI_VID_CLK_CNTL[4] = DIV12_EN

Update the bits accordingly so we will enable the bits in the correct
register once we switch these clocks to be mutable.

Fixes: 6cb57c678bb70e ("clk: meson: meson8b: add the read-only video clock trees")
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20200417184127.1319871-4-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Fix the polarity of the RESET_N lines

2020-04-29T08:26:53+00:00

CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means:
- asserting them requires setting the register value to 0
- de-asserting them requires setting the register value to 1

Set the register value accordingly for these two reset lines by setting
the inverted the register value compared to all other reset lines.

Fixes: 189621726bc2f6 ("clk: meson: meson8b: register the built-in reset controller")
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20200417184127.1319871-3-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Fix the first parent of vid_pll_in_sel

2020-04-29T08:26:53+00:00

Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not
easy to see that the vendor kernel does the same, but it actually does.
meson_clk_pll_ops in mainline still cannot fully recalculate all rates
from the HDMI PLL registers because some register bits (at the time of
writing it's unknown which bits are used for this) double the HDMI PLL
output rate (compared to simply considering M, N and FRAC) for some (but
not all) PLL settings.

Update the vid_pll_in_sel parent so our clock calculation works for
simple clock settings like the CVBS output (where no rate doubling is
going on). The PLL ops need to be fixed later on for more complex clock
settings (all HDMI rates).

Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees")
Suggested-by: Neil Armstrong 
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20200417184127.1319871-2-martin.blumenstingl@googlemail.com

clk: meson: g12a: Prepare the GPU clock tree to change at runtime

2020-04-16T10:23:05+00:00

The "mali_0" or "mali_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1"
tree when "mali_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the mali
clock.
Also propagate set_rate requests from the gate to the divider and from
the divider to the the mux so the GPU clock frequency can be updated at
runtime (which will be required for GPU DVFS). Don't propagate rate
changes to the mux parents because we don't want to change the MPLL
clocks (these are reserved for audio).

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Acked-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20200414195031.224021-3-martin.blumenstingl@googlemail.com

clk: meson: gxbb: Prepare the GPU clock tree to change at runtime

2020-04-16T10:23:05+00:00

The "mali_0" or "mali_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1"
tree when "mali_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the mali
clock.
Also propagate set_rate requests from the gate to the divider and from
the divider to the the mux so the GPU clock frequency can be updated at
runtime (which will be required for GPU DVFS). Don't propagate rate
changes to the mux parents because we don't want to change the MPLL
clocks (these are reserved for audio).

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Acked-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20200414195031.224021-2-martin.blumenstingl@googlemail.com

clk: meson: meson8b: make the hdmi_sys clock tree mutable

2020-04-14T12:29:23+00:00

The HDMI TX controller requires the hdmi_sys clock to be enabled. Allow
changing the whole clock tree now that we know that one of our drivers
requires this.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20200330234535.3327513-3-martin.blumenstingl@googlemail.com

clk: meson8b: export the HDMI system clock

2020-04-14T12:28:34+00:00

Export the HDMI system clock (used by the HDMI transmitter) so it can be
used in the dt-bindings.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/20200330234535.3327513-2-martin.blumenstingl@googlemail.com

clk: meson: meson8b: set audio output clock hierarchy

2020-02-21T10:44:41+00:00

The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to
operate. Reflect this hierarchy in the clock tree.

Fixes: e31a1900c1ff73 ("meson: clk: Add support for clock gates")
Suggested-by: Jerome Brunet 
Signed-off-by: Martin Blumenstingl 
Reviewed-by: Neil Armstrong 
Signed-off-by: Jerome Brunet